Geometrically parameterized interconnect performance models for interconnect synthesis

Authors:
Luca Daniel;Chin Siong Ong;Sok Chay Low;Kwok Hong Lee;Jacob White
Affiliations:
University of California, Berkeley;National University of Singapore;National University of Singapore;National University of Singapore;Massachusetts Institute of Technology
Venue:
Proceedings of the 2002 international symposium on Physical design
Year:
2002

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Abstract

In this paper we describe an approach for generating geometrically-parameterized integrated-circuit interconnect models that are efficient enough for use in interconnect synthesis. The model generation approach presented is automatic, and is based on a multi-parameter model-reduction algorithm. The effectiveness of the technique is tested using a multi-line bus example, where both wire spacing and wire width are considered as geometric parameters. Experimental results demonstrate that the generated models accurately predict both delay and cross-talk effects over a wide range of spacing and width variation.