An efficient Lyapunov equation-based approach for generating reduced-order models of interconnect
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Model order-reduction of RC(L) interconnect including variational analysis
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Geometrically parameterized interconnect performance models for interconnect synthesis
Proceedings of the 2002 international symposium on Physical design
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Poor Man's TBR: A Simple Model Reduction Scheme
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Analog Macromodeling using Kernel Methods
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
PRIMA: passive reduced-order interconnect macromodeling algorithm
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Projection-based approaches for model reduction of weakly nonlinear, time-varying systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Efficient linear circuit analysis by Pade approximation via the Lanczos process
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Parameterized model order reduction of nonlinear dynamical systems
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Random sampling of moment graph: a stochastic Krylov-reduction algorithm
Proceedings of the conference on Design, automation and test in Europe
Parameterized macromodeling for analog system-level design exploration
Proceedings of the 44th annual Design Automation Conference
SPARE: a Scalable algorithm for passive, structure preserving, Parameter-Aware model order REduction
Proceedings of the conference on Design, automation and test in Europe
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Fast variational interconnect delay and slew computation using quadratic models
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
ARMS - automatic residue-minimization based sampling for multi-point modeling techniques
Proceedings of the 46th Annual Design Automation Conference
A parameterized mask model for lithography simulation
Proceedings of the 46th Annual Design Automation Conference
Statistical analysis of large on-chip power grid networks by variational reduction scheme
Integration, the VLSI Journal
SPARE: a scalable algorithm for passive, structure preserving, parameter-aware model order reduction
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special issue on the 2009 ACM/IEEE international symposium on networks-on-chip
Variation-aware interconnect extraction using statistical moment preserving model order reduction
Proceedings of the Conference on Design, Automation and Test in Europe
HORUS - high-dimensional model order reduction via low moment-matching upgraded sampling
Proceedings of the Conference on Design, Automation and Test in Europe
On the efficient reduction of complete EM based parametric models
Proceedings of the Conference on Design, Automation and Test in Europe
Efficient power grid integrity analysis using on-the-fly error check and reduction
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Performance-oriented parameter dimension reduction of VLSI circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Interpolatory Projection Methods for Parameterized Model Reduction
SIAM Journal on Scientific Computing
Model order reduction of fully parameterized systems by recursive least square optimization
Proceedings of the International Conference on Computer-Aided Design
3POr: parallel projection based parameterized order reduction for multi-dimensional linear models
Proceedings of the International Conference on Computer-Aided Design
Fast timing analysis of clock networks considering environmental uncertainty
Integration, the VLSI Journal
| Hi-index | 0.00 |
We demonstrate an algorithm for interconnect modeling in the presence of process variation based on extension of the truncated balanced realization model reduction algorithm to multi-dimensional, parameter varying systems. Our scheme, based on a set of estimators of the variational TBR projection spaces, is simple to implement, contains embedded error estimators, and leads to nearly optimally sized models.