h-gamma: an RC delay metric based on a gamma distribution approximation of the homogeneous response
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Model order-reduction of RC(L) interconnect including variational analysis
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Delay and slew metrics using the lognormal distribution
Proceedings of the 40th annual Design Automation Conference
Simple metrics for slew rate of RC circuits based on two circuit moments
Proceedings of the 40th annual Design Automation Conference
First-order incremental block-based statistical timing analysis
Proceedings of the 41st annual Design Automation Conference
Variational delay metrics for interconnect timing analysis
Proceedings of the 41st annual Design Automation Conference
Statistical Timing Analysis Considering Spatial Correlations using a Single Pert-Like Traversal
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Modeling Interconnect Variability Using Efficient Parametric Model Order Reduction
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Correlation-aware statistical timing analysis with non-gaussian delay distributions
Proceedings of the 42nd annual Design Automation Conference
Interval-valued reduced order statistical interconnect modeling
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Variational interconnect analysis via PMTBR
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Stochastic analysis of interconnect performance in the presence of process variations
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Practical variation-aware interconnect delay and slew analysis for statistical timing verification
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
PRIMA: passive reduced-order interconnect macromodeling algorithm
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
RC delay metrics for performance optimization
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Guaranteed passive balancing transformations for model order reduction
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Closed-form expressions for extending step delay and slew metrics to ramp inputs for RC trees
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Efficient linear circuit analysis by Pade approximation via the Lanczos process
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Performance-oriented parameter dimension reduction of VLSI circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Interconnects constitute a dominant source of circuit delay for modern chip designs. The variations of critical dimensions in modern VLSI technologies lead to variability in interconnect performance that must be fully accounted for in timing verification. However, handling a multitude of inter-die/intra-die variations and assessing their impacts on circuit performance can dramatically complicate the timing analysis. In this paper, a practical interconnect delay and slew analysis technique is presented to facilitate efficient evaluation of wire performance variability. By harnessing a collection of computationally efficient procedures and closed-form formulas, process variations are directly mapped into the variability of the output delay and slew. An efficient method based on sensitivity analysis is implemented to calculate driving point models under variations for gate-level timing analysis. The proposed adjoint technique not only provides statistical performance variations of the interconnect network under analysis, but also produces delay and slew expressions parameterized in the underlying process variations in a quadratic parametric form. As such, it can be harnessed to enable statistical timing analysis while considering important statistical correlations. Our experimental results have indicated that the presented analysis is accurate regardless of location of sink nodes and it is also robust over a wide range of process variations.