Matrix computations (3rd ed.)
Model order-reduction of RC(L) interconnect including variational analysis
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Modeling Interconnect Variability Using Efficient Parametric Model Order Reduction
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Variational interconnect analysis via PMTBR
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Stochastic analysis of interconnect performance in the presence of process variations
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Reducing the Complexity of VLSI Performance Variation Modeling Via Parameter Dimension Reduction
ISQED '07 Proceedings of the 8th International Symposium on Quality Electronic Design
Fast variational interconnect delay and slew computation using quadratic models
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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To account for the growing process variability in modern VLSI technologies, circuit models parameterized in a multitude of parametric variations are becoming increasingly indispensable in robust circuit design. However, the high parameter dimensionality can introduce significant complexity and may even render variation-aware performance analysis and optimization completely intractable. We present a performance-oriented parameter dimension reduction framework to reduce the modeling complexity associated with high parameter dimensionality. Our framework has a theoretically sound statistical basis, namely, reduced rank regression (RRR) and its various extensions that we have introduced for more practical VLSI circuit modeling. For a variety of VLSI circuits including interconnects and CMOS digital circuits, it is shown that this parameter reduction framework can provide more than one order of magnitude reduction in parameter dimensionality. Such parameter reduction immediately leads to reduced simulation cost in sampling-based performance analysis, and more importantly, highly efficient parameterized subcircuit models that are instrumental in tackling the complexity of variation-tolerance VLSI system design.