CAD challenges in BioMEMS design
Proceedings of the 41st annual Design Automation Conference
Modeling Interconnect Variability Using Efficient Parametric Model Order Reduction
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Fast interval-valued statistical interconnect modeling and reduction
Proceedings of the 2005 international symposium on Physical design
A quasi-convex optimization approach to parameterized model order reduction
Proceedings of the 42nd annual Design Automation Conference
Developing design tools for biological and biomedical applications of micro- and nano-technology
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Parameter independent model order reduction
Mathematics and Computers in Simulation
Variational interconnect analysis via PMTBR
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Variational Interconnect Delay Metrics for Statistical Timing Analysis
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
SACI: statistical static timing analysis of coupled interconnects
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Parameterized model order reduction of nonlinear dynamical systems
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Efficient statistical capacitance variability modeling with orthogonal principle factor analysis
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Non-gaussian statistical interconnect timing analysis
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Thermal via allocation for 3D ICs considering temporally and spatially variant thermal power
Proceedings of the 2006 international symposium on Low power electronics and design
Empire: an efficient and compact multiple-parameterized model order reduction method
Proceedings of the 2007 international symposium on Physical design
Practical variation-aware interconnect delay and slew analysis for statistical timing verification
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Simultaneous power and thermal integrity driven via stapling in 3D ICs
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Goal-oriented, model-constrained optimization for reduction of large-scale systems
Journal of Computational Physics
Random sampling of moment graph: a stochastic Krylov-reduction algorithm
Proceedings of the conference on Design, automation and test in Europe
Statistical model order reduction for interconnect circuits considering spatial correlations
Proceedings of the conference on Design, automation and test in Europe
Parameterized macromodeling for analog system-level design exploration
Proceedings of the 44th annual Design Automation Conference
A methodology for timing model characterization for statistical static timing analysis
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Parameterized model order reduction via a two-directional Arnoldi process
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
SPARE: a Scalable algorithm for passive, structure preserving, Parameter-Aware model order REduction
Proceedings of the conference on Design, automation and test in Europe
A two-directional Arnoldi process and its application to parametric model order reduction
Journal of Computational and Applied Mathematics
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Fast variational interconnect delay and slew computation using quadratic models
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
ARMS - automatic residue-minimization based sampling for multi-point modeling techniques
Proceedings of the 46th Annual Design Automation Conference
Robust simulation methodology for surface-roughness loss in interconnect and package modelings
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Statistical analysis of large on-chip power grid networks by variational reduction scheme
Integration, the VLSI Journal
SPARE: a scalable algorithm for passive, structure preserving, parameter-aware model order reduction
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special issue on the 2009 ACM/IEEE international symposium on networks-on-chip
EMPIRE: an efficient and compact multiple-parameterized model-order reduction
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Automated compact dynamical modeling: an enabling tool for analog designers
Proceedings of the 47th Design Automation Conference
Variation-aware interconnect extraction using statistical moment preserving model order reduction
Proceedings of the Conference on Design, Automation and Test in Europe
HORUS - high-dimensional model order reduction via low moment-matching upgraded sampling
Proceedings of the Conference on Design, Automation and Test in Europe
On the efficient reduction of complete EM based parametric models
Proceedings of the Conference on Design, Automation and Test in Europe
Thermal via allocation for 3-D ICs considering temporally and spatially variant thermal power
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Performance-oriented parameter dimension reduction of VLSI circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An Online Method for Interpolating Linear Parametric Reduced-Order Models
SIAM Journal on Scientific Computing
Interpolatory Projection Methods for Parameterized Model Reduction
SIAM Journal on Scientific Computing
Model order reduction of fully parameterized systems by recursive least square optimization
Proceedings of the International Conference on Computer-Aided Design
3POr: parallel projection based parameterized order reduction for multi-dimensional linear models
Proceedings of the International Conference on Computer-Aided Design
Parametrized model reduction based on semidefinite programming
Automatica (Journal of IFAC)
Mathematics and Computers in Simulation
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In this paper, we describe an approach for generating accurate geometrically parameterized integrated circuit interconnect models that are efficient enough for use in interconnect synthesis. The model-generation approach presented is automatic, and is based on a multiparameter moment matching model-reduction algorithm. A moment-matching theorem proof for the algorithm is derived, as well as a complexity analysis for the model-order growth. The effectiveness of the technique is tested using a capacitance extraction example, where the plate spacing is considered as the geometric parameter, and a multiline bus example, where both wire spacing and wire width are considered as geometric parameters. Experimental results demonstrate that the generated models accurately predict capacitance values for the capacitor example, and both delay and cross-talk effects over a reasonably wide range of spacing and width variation for the multiline bus example.