Reduced-order modeling of large linear subcircuits via a block Lanczos algorithm
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Model order-reduction of RC(L) interconnect including variational analysis
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Interval-valued reduced order statistical interconnect modeling
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Variational interconnect analysis via PMTBR
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Stochastic analysis of interconnect performance in the presence of process variations
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
PRIMA: passive reduced-order interconnect macromodeling algorithm
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Efficient linear circuit analysis by Pade approximation via the Lanczos process
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
SPARE: a Scalable algorithm for passive, structure preserving, Parameter-Aware model order REduction
Proceedings of the conference on Design, automation and test in Europe
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
ARMS - automatic residue-minimization based sampling for multi-point modeling techniques
Proceedings of the 46th Annual Design Automation Conference
Statistical analysis of large on-chip power grid networks by variational reduction scheme
Integration, the VLSI Journal
SPARE: a scalable algorithm for passive, structure preserving, parameter-aware model order reduction
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special issue on the 2009 ACM/IEEE international symposium on networks-on-chip
Automated compact dynamical modeling: an enabling tool for analog designers
Proceedings of the 47th Design Automation Conference
HORUS - high-dimensional model order reduction via low moment-matching upgraded sampling
Proceedings of the Conference on Design, Automation and Test in Europe
On the efficient reduction of complete EM based parametric models
Proceedings of the Conference on Design, Automation and Test in Europe
3POr: parallel projection based parameterized order reduction for multi-dimensional linear models
Proceedings of the International Conference on Computer-Aided Design
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In this paper we introduce a new algorithm for model order reduction in the presence of parameter or process variation. Our analysis is performed using a graph interpretation of the multi-parameter moment matching approach, leading to a computational technique based on Random Sampling of Moment Graph (RSMG). Using this technique, we have developed a new algorithm that combines the best aspects of recently proposed parameterized moment-matching and approximate TBR procedures. RSMG attempts to avoid both exponential growth of computational complexity and multiple matrix factorizations, the primary drawbacks of existing methods, and illustrates good ability to tailor algorithms to apply computational effort where needed. Industry examples are used to verify our new algorithms.