Model order-reduction of RC(L) interconnect including variational analysis
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Extended Krylov subspace method for reduced order analysis of linear circuits with multiple sources
Proceedings of the 37th Annual Design Automation Conference
Modeling and analysis of leakage power considering within-die process variations
Proceedings of the 2002 international symposium on Low power electronics and design
Proceedings of the 40th annual Design Automation Conference
Poor Man's TBR: A Simple Model Reduction Scheme
Proceedings of the conference on Design, automation and test in Europe - Volume 2
A stochastic approach To power grid analysis
Proceedings of the 41st annual Design Automation Conference
Statistical Verification of Power Grids Considering Process-Induced Leakage Current Variations
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Stochastic Power Grid Analysis Considering Process Variations
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Variational interconnect analysis via PMTBR
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Static timing analysis considering power supply variations
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Stochastic variational analysis of large power grids considering intra-die correlations
Proceedings of the 43rd annual Design Automation Conference
Design for Manufacturability and Yield for Nano-Scale CMOS
Design for Manufacturability and Yield for Nano-Scale CMOS
Advanced Model Order Reduction Techniques in VLSI Design
Advanced Model Order Reduction Techniques in VLSI Design
An Introduction to Parallel and Vector Scientific Computation (Cambridge Texts in Applied Mathematics)
Random sampling of moment graph: a stochastic Krylov-reduction algorithm
Proceedings of the conference on Design, automation and test in Europe
Next-Generation Design and EDA Challenges: Small Physics, Big Systems, and Tall Tool-Chains
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
Stochastic extended Krylov subspace method for variational analysis of on-chip power grid networks
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Power grid analysis benchmarks
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
ETBR: extended truncated balanced realization method for on-chip power grid network analysis
Proceedings of the conference on Design, automation and test in Europe
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Electronic Circuit & System Simulation Methods (SRE)
Electronic Circuit & System Simulation Methods (SRE)
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Poor man's TBR: a simple model reduction scheme
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Fast Variational Analysis of On-Chip Power Grids by Stochastic Extended Krylov Subspace Method
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Integrated circuit security techniques using variable supply voltage
Proceedings of the 48th Design Automation Conference
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One of the most critical challenges in today's CMOS VLSI design is the lack of predictability in chip performance at design stage. One of the process variabilities comes from the voltage drop variations in on-chip power distribution networks. In this paper, we present a novel analysis approach for computing voltage drops of large power grid networks under process variations. The new algorithm is very efficient and scalable for huge networks with a large number of variational variables. This approach, called variational extended truncated balanced realization (varETBR), is based on model order reduction techniques to reduce the circuit matrices before the variational simulation. It performs the parameterized reduction on the original system using variation-bearing subspaces. After the reduction, Monte Carlo based statistical simulation is performed on the reduced system and the statistical responses of the original system are obtained thereafter. varETBR calculates variational response Grammians by Monte Carlo based numerical integration considering both system and input source variations in generating the projection subspace. varETBR is very scalable for the number of variables and flexible for different variational distributions and ranges as demonstrated in experimental results. Experimental results, on a number of IBM benchmark circuits up to 1.6 million nodes, show that the varETBR can be 1900X faster than the Monte Carlo method and is much more scalable than one of the recently proposed approaches.