Proceedings of the 2006 international symposium on Physical design
SMM: Scalable Analysis of Power Delivery Networks by Stochastic Moment Matching
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Large power grid analysis using domain decomposition
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Proceedings of the 43rd annual Design Automation Conference
Stochastic extended Krylov subspace method for variational analysis of on-chip power grid networks
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Parallel domain decomposition for simulation of large-scale power grids
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Hierarchical Krylov subspace reduced order modeling of large RLC circuits
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
ETBR: extended truncated balanced realization method for on-chip power grid network analysis
Proceedings of the conference on Design, automation and test in Europe
Hierarchical Krylov subspace based reduction of large interconnects
Integration, the VLSI Journal
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Stochastic power/ground supply voltage prediction and optimization via analytical placement
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Adaptive circuit block model for power supply noise analysis of low power system-an-chip
SOC'09 Proceedings of the 11th international conference on System-on-chip
Statistical analysis of large on-chip power grid networks by variational reduction scheme
Integration, the VLSI Journal
Efficient power grid integrity analysis using on-the-fly error check and reduction
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Vectorless verification of RLC power grids with transient current constraints
Proceedings of the International Conference on Computer-Aided Design
Incremental power grid verification
Proceedings of the 49th Annual Design Automation Conference
Deterministic random walk preconditioning for power grid analysis
Proceedings of the International Conference on Computer-Aided Design
Scalable power grid transient analysis via MOR-assisted time-domain simulations
Proceedings of the International Conference on Computer-Aided Design
Parallel power grid analysis using preconditioned GMRES solver on CPU-GPU platforms
Proceedings of the International Conference on Computer-Aided Design
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This paper proposes a general hierarchical analysis methodology, HiPRIME, to efficiently analyze RLKC power delivery systems. After partitioning the circuits into blocks, we develop and apply the IEKS (Improved Extended Krylov Subspace) method to build the multiport Norton equivalent circuits which transform all the internal sources to Norton current sources at ports. Since there are no active elements inside the Norton circuits, passive or realizable model order reduction techniques such as PRIMA can be applied. The significant speed improvement, 700 times faster than Spice with less than 0.2% error and 7 times faster than a state-of-the-art solver, InductWise, is observed. To further reduce the top-level hierarchy runtime, we develop a second-level model reduction algorithm and prove its passivity.