Partitioning and reduction of RC interconnect networks based on scattering parameter macromodels
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
A static pattern-independent technique for power grid voltage integrity verification
Proceedings of the 40th annual Design Automation Conference
Power grid voltage integrity verification
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
Incremental partitioning-based vectorless power grid verification
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
A geometric approach for early power grid verification using current constraints
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Fast vectorless power grid verification using an approximate inverse technique
Proceedings of the 46th Annual Design Automation Conference
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Realizable Reduction of RC Networks
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Overview of vectorless/early power grid verification
Proceedings of the International Conference on Computer-Aided Design
Constraint abstraction for vectorless power grid verification
Proceedings of the 50th Annual Design Automation Conference
Incremental transient simulation of power grid
Proceedings of the 2014 on International symposium on physical design
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Verification of the on-die power grid is a key step in the design of complex high-performance integrated circuits. For the very large grids in modern designs, incremental verification is highly desirable, because it allows one to skip the verification of a certain section of the grid (internal nodes) and instead, verify only the rest of the grid (external nodes). We propose an efficient approach for incremental verification in the context of vectorless constraints-based grid verification, under dynamic conditions. The traditional difficulty is that the dynamic case requires iterative analysis of both the internal and external sections. This has been previously overcome for simulation purposes, but we provide the first solution for verification, through two key contributions: 1) a bound on the internal nodes' voltages is developed that eliminates the need for iterative analysis, and 2) a multi-port Norton approach is used to construct a reduced macromodel for the internal section. As a result, we demonstrate significant reductions in runtime, with speed-ups in the range of 3-8x, with negligible impact on accuracy.