DAC '96 Proceedings of the 33rd annual Design Automation Conference
Model order-reduction of RC(L) interconnect including variational analysis
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Proceedings of the 37th Annual Design Automation Conference
Efficient and passive modeling of transmission lines by using differential quadrature method
Proceedings of the conference on Design, automation and test in Europe
Novel interconnect modeling by using high-order compact finite difference methods
Proceedings of the 12th ACM Great Lakes symposium on VLSI
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Efficient Macromodeling for On-Chip Interconnects
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Hybrid Reduction Technique for Efficient Simulation of Linear/Nonlinear Mixed Circuits
Proceedings of the conference on Design, automation and test in Europe - Volume 2
A linear fractional transform (LFT) based model for interconnect parametric uncertainty
Proceedings of the 41st annual Design Automation Conference
Passive Hierarchical Model Order Reduction and Realization of RLCM Circuits
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
EFFICIENT THERMAL SIMULATION FOR RUN-TIME TEMPERATURE TRACKING AND MANAGEMENT
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Stochastic analysis of interconnect performance in the presence of process variations
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Proceedings of the 43rd annual Design Automation Conference
Hierarchical Krylov subspace reduced order modeling of large RLC circuits
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Multiple block structure-preserving reduced order modeling of interconnect circuits
Integration, the VLSI Journal
Hierarchical Krylov subspace based reduction of large interconnects
Integration, the VLSI Journal
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Sparse and Passive Reduced-Order Interconnect Modeling by Eigenspace Method
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Analytical timing model for inductance-dominant interconnect based on traveling wave propagation
Microelectronics Journal
Equivalent-circuit interconnect modeling based on the fifth-order differential quadrature methods
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Incremental power grid verification
Proceedings of the 49th Annual Design Automation Conference
Proceedings of the 49th Annual Design Automation Conference
Fast timing analysis of clock networks considering environmental uncertainty
Integration, the VLSI Journal
Journal of Computational and Applied Mathematics
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A novel technique is presented which employs pole analysis via congruence transformations (PACT) to reduce RC networks in a well-conditioned manner. Pole analysis is shown to be more efficient than Pade approximations when the number of network ports is large, and congruence transformations preserve the passivity (and thus absolute stability) of the networks. The error incurred by reducing the networks is shown to be bounded by values which are fully selectable by the user. Networks are represented by admittance matrices throughout the analysis, and this representation both simplifies interfacing the reduced networks with circuit simulators and facilitates realization of the reduced networks using RC elements. A prototype SPICE-in, SPICE-out, network reduction CAD tool called RCFIT is detailed, and examples are presented which demonstrate the accuracy and efficiency of the PACT algorithm