An efficient Lyapunov equation-based approach for generating reduced-order models of interconnect
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Model order-reduction of RC(L) interconnect including variational analysis
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Efficient model reduction of interconnect via approximate system gramians
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Balanced truncation with spectral shaping for RLC interconnects
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Linear Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
PRIMA: passive reduced-order interconnect macromodeling algorithm
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Efficient linear circuit analysis by Pade approximation via the Lanczos process
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Geometrically parameterized interconnect performance models for interconnect synthesis
Proceedings of the 2002 international symposium on Physical design
Poor Man's TBR: A Simple Model Reduction Scheme
Proceedings of the conference on Design, automation and test in Europe - Volume 2
A linear fractional transform (LFT) based model for interconnect parametric uncertainty
Proceedings of the 41st annual Design Automation Conference
Modeling Interconnect Variability Using Efficient Parametric Model Order Reduction
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
A quasi-convex optimization approach to parameterized model order reduction
Proceedings of the 42nd annual Design Automation Conference
Variational interconnect analysis via PMTBR
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Stochastic analysis of interconnect performance in the presence of process variations
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Parameterized model order reduction of nonlinear dynamical systems
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Deep submicron interconnect timing model with quadratic random variable analysis
Proceedings of the conference on Design, automation and test in Europe
Fast variational interconnect delay and slew computation using quadratic models
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
SPARE: a scalable algorithm for passive, structure preserving, parameter-aware model order reduction
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special issue on the 2009 ACM/IEEE international symposium on networks-on-chip
Performance-oriented parameter dimension reduction of VLSI circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Model order reduction of fully parameterized systems by recursive least square optimization
Proceedings of the International Conference on Computer-Aided Design
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This paper presents a spectrally-weighted balanced truncation technique for RLC interconnects, a technique needed when the interconnect circuit parameters change as a result of variations in the manufacturing process. The salient features of this algorithm are the inclusion of parameter variations in the RLC interconnect, the guaranteed stability of the reduced transfer function, and the availability of provable frequency-weighted error bounds for the reduced-order system. This paper shows that the balanced truncation technique is an effective model-order reduction technique when variations in the circuit parameters are taken into consideration. Experimental results show that the new variational spectrally-weighted balanced truncation attains, on average, 20% more accuracy than the variational Krylov-subspace-based model-order reduction techniques while the run-time is also, on average, 5% faster.