Noise in deep submicron digital design
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Global harmony: coupled noise analysis for full-chip RC interconnect networks
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Getting to the bottom of deep submicron
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
On switch factor based analysis of coupled RC interconnects
Proceedings of the 37th Annual Design Automation Conference
Balanced truncation with spectral shaping for RLC interconnects
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Methods for Calculating Coupling Noise in Early Design: A Comparative Analysis
ICCD '98 Proceedings of the International Conference on Computer Design
Noise Model for Multiple Segmented Coupled RC Interconnects
ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
Analytic Modeling of Interconnects for Deep Sub-Micron Circuits
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Design Methodologies and Architecture Solutions for High-Performance Interconnects
ICCD '04 Proceedings of the IEEE International Conference on Computer Design
Neural Networks, Fuzzy Logic and Genetic Algorithms
Neural Networks, Fuzzy Logic and Genetic Algorithms
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
TIGER: an efficient timing-driven global router for gate array and standard cell layout design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
PRIMA: passive reduced-order interconnect macromodeling algorithm
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Asymptotic waveform evaluation for timing analysis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Crosstalk in VLSI interconnections
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Exact and efficient crosstalk estimation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Capacitive coupling noise in high-speed VLSI circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Efficient linear circuit analysis by Pade approximation via the Lanczos process
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This paper describes a novel yet highly efficient approach for estimating the time-domain response of capacitive coupled distributed RC interconnects. By using this method, the voltage signal at any particular point in such wires can be accurately and quickly obtained with very low computational cost. The proposed model exhibits a very good agreement with HSPICE simulations with worst-case error less than 3% and can be readily implemented in CAD analysis tools. This paper also presents an efficient model to estimate the capacitive crosstalk in high-speed very large scale integration (VLSI) circuits. Experimental results show that the maximum error of our peak noise predictions is less than 2.5%. In addition, this work presents an efficient artificial neural network (ANN)-based technique for modeling the time-domain response of interconnects and crosstalk noise. While existing fast noise estimation metrics may overestimate or underestimate the coupling noise, the simulation results demonstrate the ability of this approach to successfully predict coupling noise with a very good accuracy as compared to HSPICE in modest CPU times. Thereby, the proposed models and techniques can be used to predict the signal integrity for designing high-speed and high-density VLSI circuits.