Combinatorial optimization: algorithms and complexity
Combinatorial optimization: algorithms and complexity
Integer and combinatorial optimization
Integer and combinatorial optimization
AWESpice: a general tool for the accurate and efficient simulation of interconnect problems
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Oblique Projection Methods for Large Scale Model Reduction
SIAM Journal on Matrix Analysis and Applications
Reduced-order modeling of large linear subcircuits via a block Lanczos algorithm
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Software for simplified Lanczos and QMR algorithms
Applied Numerical Mathematics - Special issue on iterative methods for linear equations
Reduced-order modeling of large passive linear circuits by means of the SYPVL algorithm
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Noise in deep submicron digital design
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Zeros and passivity of Arnoldi-reduced-order models for interconnect networks
DAC '97 Proceedings of the 34th annual Design Automation Conference
Design methodology for the S/390 parallel enterprise server G4 microprocessors
IBM Journal of Research and Development - Special issue: IBM S/390 G3 and G4
AWE macromodels of VLSI interconnect for circuit simulation
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Lanczos Algorithms for Large Symmetric Eigenvalue Computations, Vol. 1
Lanczos Algorithms for Large Symmetric Eigenvalue Computations, Vol. 1
Efficient linear circuit analysis by Pade approximation via the Lanczos process
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Design methodology for the S/390 parallel enterprise server G4 microprocessors
IBM Journal of Research and Development - Special issue: IBM S/390 G3 and G4
Design methodologies for noise in digital integrated circuits
DAC '98 Proceedings of the 35th annual Design Automation Conference
Energy-efficiency in presence of deep submicron noise
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
The deep sub-micron signal integrity challenge
ISPD '99 Proceedings of the 1999 international symposium on Physical design
Chip-level verification for parasitic coupling effects in deep-submicron digital designs
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Projective convolution: RLC model-order reduction using the impulse response
DATE '99 Proceedings of the conference on Design, automation and test in Europe
ENOR: model order reduction of RLC circuits using nodal equations for efficient factorization
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
ClariNet: a noise analysis tool for deep submicron design
Proceedings of the 37th Annual Design Automation Conference
Critical path analysis using a dynamically bounded delay model
Proceedings of the 37th Annual Design Automation Conference
TACO: timing analysis with coupling
Proceedings of the 37th Annual Design Automation Conference
Towards true crosstalk noise analysis
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Interconnect parasitic extraction in the digital IC design methodology
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Proceedings of the conference on Design, automation and test in Europe
Driver modeling and alignment for worst-case delay noise
Proceedings of the 38th annual Design Automation Conference
On convergence of switching windows computation in presence of crosstalk noise
Proceedings of the 2002 international symposium on Physical design
Proceedings of the 39th annual Design Automation Conference
False-noise analysis using logic implications
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Efficient switching window computation for cross-talk noise
Proceedings of the 8th ACM/IEEE international workshop on Timing issues in the specification and synthesis of digital systems
Miller factor for gate-level coupling delay calculation
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Full-chip, three-dimensional, shapes-based RLC extraction
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Switching window computation for static timing analysis in presence of crosstalk noise
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
On the signal bounding problem in timing analysis
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
False-noise analysis using logic implications
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Practical considerations in RLCK crosstalk analysis for digital integrated circuits
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Conquering Noise in Deep-Submicron Digital ICs
IEEE Design & Test
Estimation of signal arrival times in the presence of delay noise
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Cross-Coupled Noise Propagation in VLSI Designs
Analog Integrated Circuits and Signal Processing
Interconnect Geometry Optimization Using Modular Artificial Neural Networks
Analog Integrated Circuits and Signal Processing
Behavioral Transformations to Increase Noise Immunity in Asynchronous Specifications
ASYNC '99 Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems
Noise Model for Multiple Segmented Coupled RC Interconnects
ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
New Efficient and Accurate Moment Matching Based Model for Crosstalk Estimation in Coupled RC Trees
ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
Driver modeling and alignment for worst-case delay noise
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Modeling the Non-Linear Behavior of Library Cells for an Accurate Static Noise Analysis
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Noise Library Characterization for Large Capacity Static Noise Analysis Tools
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
A complete methodology for an accurate static noise analysis
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Crosstalk analysis using reconvergence correlation
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Pessimism reduction in crosstalk noise aware STA
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
A non-iterative continuous model for switching window computation with crosstalk noise
Microelectronic Engineering
Top-k aggressors sets in delay noise analysis
Proceedings of the 44th annual Design Automation Conference
Victim alignment in crosstalk-aware timing analysis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Interconnect performance corners considering crosstalk noise
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
Crosstalk pulsewidth calculation
Microelectronics Journal
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Noise is becoming one of the most important metrics in the design of VLSI systems, certainly of comparable importance to area, timing, and power. In this paper, we describe Global Harmony, a methodology for the analysis of coupling noise in the global interconnect of large VLSI chips, being developed for the design of high-performance microprocessors. The architecture of Global Harmony involves a careful combination of static noise analysis, static timing analysis, and reduced-order modelling techniques. We describe a reduced-order modelling approach that allows for passive multiport reduction of RC netlists as impedance macromodels while preserving the symmetry and sparsity of the state matrices for efficient storage. We describe how the macromodels are practically employed to perform coupling analysis and how timing constraints can be used to limit pessimism in the analysis.