Chip-level verification for parasitic coupling effects in deep-submicron digital designs

Reduced-order modeling of large linear subcircuits via a block Lanczos algorithm

DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference

Noise in deep submicron digital design

Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design

Digital sensitivity: predicting signal interaction using functional analysis

Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design

Global harmony: coupled noise analysis for full-chip RC interconnect networks

ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design

Efficient coupled noise estimation for on-chip interconnects

ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design

Chip hierarchical design system (CHDS): a foundation for timing-driven physical design into the 21st century

Proceedings of the 1997 international symposium on Physical design

Reduced-order modeling of large linear passive multi-terminal circuits using matrix-padé approximation

Proceedings of the conference on Design, automation and test in Europe

Performance computation for precharacterized CMOS gates with RC loads

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Crosstalk reduction for VLSI

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems