Don't cares in multi-level network optimization
Don't cares in multi-level network optimization
Techniques for crosstalk avoidance in the physical design of high-performance digital systems
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Test Generation for Path Delay Faults Using Binary Decision Diagrams
IEEE Transactions on Computers
A roadmap of CAD tool changes for sub-micron interconnect problems
Proceedings of the 1997 international symposium on Physical design
Timing and crosstalk driven area routing
DAC '98 Proceedings of the 35th annual Design Automation Conference
Chip-level verification for parasitic coupling effects in deep-submicron digital designs
DATE '99 Proceedings of the conference on Design, automation and test in Europe
A novel VLSI layout fabric for deep sub-micron applications
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Domino logic synthesis minimizing crosstalk
Proceedings of the 37th Annual Design Automation Conference
Functional correlation analysis in crosstalk induced critical paths identification
Proceedings of the 38th annual Design Automation Conference
False coupling interactions in static timing analysis
Proceedings of the 38th annual Design Automation Conference
False-noise analysis using logic implications
ACM Transactions on Design Automation of Electronic Systems (TODAES)
False-noise analysis using logic implications
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Estimation of signal arrival times in the presence of delay noise
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Temporofunctional crosstalk noise analysis
Proceedings of the 40th annual Design Automation Conference
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Behavioral Transformations to Increase Noise Immunity in Asynchronous Specifications
ASYNC '99 Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems
Using Temporal Constraints for Eliminating Crosstalk Candidates for Design and Test
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
False-Noise Analysis for Domino Circuits
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Interconnect design methods for memory design
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Functions for Quality Transition Fault Tests
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Crosstalk-aware domino logic synthesis
Proceedings of the conference on Design, automation and test in Europe: Proceedings
On the Use of ZBDDs for Implicit and Compact Critical Path Delay Fault Test Generation
Journal of Electronic Testing: Theory and Applications
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Maintaining signal integrity in digital systems is becoming increasingly difficult due to the rising number of analog effects seen in deep submicron design. One such effect, the signal crosstalk problem, is now a serious design concern. Signals which couple electrically may not affect system behavior because of timing or function in the digital domain. If we can isolate observable coupling effects then we can constrain layout synthesis to eliminate them. In this paper, we find that it is possible to predict signal interaction by signal functionality alone, leading to a significant amount of robust switching isolation, independent of parasitics introduced by layout or semiconductor process. We introduce techniques to predict signal interaction using functional sensitivity analysis. In general sequential networks we find that significant switching isolation can be extracted with efficient sensitivity analysis algorithms, thus giving promise to the goal of synthesizing layout free from crosstalk effects.