New algorithms for gate sizing: a comparative study
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Digital sensitivity: predicting signal interaction using functional analysis
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Gate sizing for constrained delay/power/area optimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
Buffer insertion with accurate gate and interconnect delay computation
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Towards true crosstalk noise analysis
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Conquering Noise in Deep-Submicron Digital ICs
IEEE Design & Test
Gate Sizing: A General Purpose Optimization Approach
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Worst Delay Estimation in Crosstalk Aware Static Timing Analysis
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
Efficient Delay Calculation in Presence of Crosstalk
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
Classification and identification of nonrobust untestable path delay faults
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Buffer insertion for noise and delay optimization
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Temporofunctional crosstalk noise analysis
Proceedings of the 40th annual Design Automation Conference
Timing macro-modeling of IP blocks with crosstalk
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Trade-off between latch and flop for min-period sequential circuit designs with crosstalk
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Constrained aggressor set selection for maximum coupling noise
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Feasible aggressor-set identification under constraints for maximum coupling noise
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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In deep submicron digital circuits capacitive couplings make delay of a switching signal highly dependent on its neighbors switching times and switching directions. A long path may have a large num-ber of coupling neighbors with difficult to determine interdepen-dencies. Ignoring the mutual relationship among the signals may result in a very pessimistic estimation of circuit delay. In this paper, we apply efficient functional correlation analysis techniques to identify critical paths caused by crosstalk delay effects. We also discuss applications to static timing optimization. Experiments demonstrate efficacy of the proposed technique.