Calculating worst-case gate delays due to dominant capacitance coupling
DAC '97 Proceedings of the 34th annual Design Automation Conference
Timing analysis and optimization (tutorial): from devices to systems
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Determination of worst-case aggressor alignment for delay calculation
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Towards true crosstalk noise analysis
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Capturing the Effect of Crosstalk on Delay
VLSID '00 Proceedings of the 13th International Conference on VLSI Design
Efficient Delay Calculation in Presence of Crosstalk
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
Crosstalk Aware Static Timing Analysis: A Two Step Approach
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
Functional correlation analysis in crosstalk induced critical paths identification
Proceedings of the 38th annual Design Automation Conference
On convergence of switching windows computation in presence of crosstalk noise
Proceedings of the 2002 international symposium on Physical design
Static noise analysis with noise windows
Proceedings of the 40th annual Design Automation Conference
Eliminating False Positives in Crosstalk Noise Analysis
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Sensitivity-Based Gate Delay Propagation in Static Timing Analysis
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Pessimism reduction in crosstalk noise aware STA
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Top-k aggressors sets in delay noise analysis
Proceedings of the 44th annual Design Automation Conference
Victim alignment in crosstalk aware timing analysis
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
A noniterative equivalent waveform model for timing analysis in presence of crosstalk
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Victim alignment in crosstalk-aware timing analysis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Digital circuits manufactured in deep sub-micron technologies may experience crosstalk induced delay and noise signals. Crosstalk induced delay can be quite significant and difficult to determine because of dependency on switching time of the neighboring signals. We study the problem of computing signal earliest and latest arrival time when timing windows and slew rate ranges of the inputs and coupling neighbors' inputs are known. We propose a complexity O(nlogn) algorithm to solve this problem. The proposed method has been applied in crosstalk aware static timing analysis to guide timing driven layout synthesis. Experimental results have demonstrated its efficacy and efficiency.