Determination of worst-case aggressor alignment for delay calculation
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Static timing analysis taking crosstallk into account
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Driver modeling and alignment for worst-case delay noise
Proceedings of the 38th annual Design Automation Conference
Switching window computation for static timing analysis in presence of crosstalk noise
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Worst Delay Estimation in Crosstalk Aware Static Timing Analysis
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
Slope propagation in static timing analysis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Equivalent waveform propagation for static timing analysis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
CGTA: current gain-based timing analysis for logic cells
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Cell delay analysis based on rate-of-current change
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Current source based standard cell model for accurate signal integrity and timing analysis
Proceedings of the conference on Design, automation and test in Europe
A moment-based effective characterization waveform for static timing analysis
Proceedings of the 46th Annual Design Automation Conference
PATMOS'10 Proceedings of the 20th international conference on Integrated circuit and system design: power and timing modeling, optimization and simulation
Proceedings of the 49th Annual Design Automation Conference
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This paper presents a methodology for accurate propagation of delay information through a gate for the purpose of static timing analysis (STA) in the presence of noise. Conventional STA tools represent an electrical waveform at the intermediate node of a logic circuit by its arrival time and slope. In general these two parameters are calculated based on the time instances at which the input waveform passes through predetermined voltage levels. However, to properly account for the impact of noise on the shape of a waveform, it is insufficient to model the waveform by using only two parameters. The key contribution of the proposed methodology is to base the timing analysis on the sensitivity of the output to input waveforms and accurately, yet efficiently, propagate equivalent electrical waveforms throughout a VLSI circuit. A hybrid technique combines the sensitivity-based approach with an energy-based technique to increase the efficiency of gate delay propagation. Experimental results demonstrate higher accuracy of our methodology compared to the best of the existing techniques. The sensitivity-based technique is compatible with the current level of gate characterization in conventional ASIC cell libraries, and so it can be easily incorporated into the commercial STA tools to enhance their accuracy.