Global harmony: coupled noise analysis for full-chip RC interconnect networks
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Design methodologies for noise in digital integrated circuits
DAC '98 Proceedings of the 35th annual Design Automation Conference
Determination of worst-case aggressor alignment for delay calculation
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
On switch factor based analysis of coupled RC interconnects
Proceedings of the 37th Annual Design Automation Conference
TACO: timing analysis with coupling
Proceedings of the 37th Annual Design Automation Conference
Towards true crosstalk noise analysis
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Logic Synthesis and Optimization
Logic Synthesis and Optimization
Miller factor for gate-level coupling delay calculation
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Deep Sub-Micron Static Timing Analysis in Presence of Crosstalk
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
Crosstalk Aware Static Timing Analysis: A Two Step Approach
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
The implications of deep sub-micron technology on the design of high performance digital vlsi systems
Timing analysis with crosstalk as fixpoints on complete lattice
Proceedings of the 38th annual Design Automation Conference
On convergence of switching windows computation in presence of crosstalk noise
Proceedings of the 2002 international symposium on Physical design
Timed pattern generation for noise-on-delay calculation
Proceedings of the 39th annual Design Automation Conference
From blind certainty to informed uncertainty
Proceedings of the 8th ACM/IEEE international workshop on Timing issues in the specification and synthesis of digital systems
Clock schedule verification with crosstalk
Proceedings of the 8th ACM/IEEE international workshop on Timing issues in the specification and synthesis of digital systems
Efficient switching window computation for cross-talk noise
Proceedings of the 8th ACM/IEEE international workshop on Timing issues in the specification and synthesis of digital systems
Refining switching window by time slots for crosstalk noise calculation
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Non-iterative switching window computation for delay-noise
Proceedings of the 40th annual Design Automation Conference
Crosstalk Test Generation on Pseudo industrial Circuits: A Case Study
ITC '01 Proceedings of the 2001 IEEE International Test Conference
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Driver modeling and alignment for worst-case delay noise
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
RESTA: a robust and extendable symbolic timing analysis tool
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Timing Verification with Crosstalk for Transparently Latched Circuits
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Sensitivity-Based Gate Delay Propagation in Static Timing Analysis
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
An empirical study of crosstalk in VDSM technologies
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Timing macro-modeling of IP blocks with crosstalk
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Trade-off between latch and flop for min-period sequential circuit designs with crosstalk
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Pessimism reduction in crosstalk noise aware STA
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
A non-iterative continuous model for switching window computation with crosstalk noise
Microelectronic Engineering
Accurate timing analysis using SAT and pattern-dependent delay models
Proceedings of the conference on Design, automation and test in Europe
A noniterative equivalent waveform model for timing analysis in presence of crosstalk
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Pessimism reduction in coupling-aware static timing analysis using timing and logic filtering
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Pessimism reduction in coupling-aware static timing analysis using timing and logic filtering
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
FA-STAC: An algorithmic framework for fast and accurate coupling aware static timing analysis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Test Vector Generation for Post-Silicon Delay Testing Using SAT-Based Decision Problems
Journal of Electronic Testing: Theory and Applications
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Crosstalk effect is crucial for timing analysis in very deep submicron design. In this paper, we present and compare multiple scheduling algorithms to compute switching windows for static timing analysis in presence of crosstalk noise. We also introduce an efficient technique to evaluate the worst case alignment of multiple aggressors.