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Proceedings of the 39th annual Design Automation Conference
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Proceedings of the 39th annual Design Automation Conference
Logic Synthesis and Verification
Logic Synthesis and Verification
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Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Timing Yield Estimation from Static Timing Analysis
ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
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Proceedings of the 41st annual Design Automation Conference
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Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
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Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
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Proceedings of the conference on Design, automation and test in Europe
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International Journal of Embedded and Real-Time Communication Systems
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The accuracy, computational efficiency, and reliability of static timing analysis have made it the workhorse for verifying the timing of synchronous digital integrated circuits for more than a decade. In this paper we charge that the traditional deterministic approach to analyzing the timing of circuits is significantly undermining its accuracy and may even challenge its reliability. We argue that computation of the static timing of a circuit requires a dramatic rethinking in order to continue serving its role as an enabler of high-performance designs. More fundamentally we believe that for circuits to be reliably designed the underlying probabilistic effects must be brought to the forefront of design and no longer hidden under conservative approximations. The reasons that justify such a radical transition are presented together with directions for solutions.