Fundamentals of modern VLSI devices
Fundamentals of modern VLSI devices
Technology and design challenges for low power and high performance
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
From blind certainty to informed uncertainty
Proceedings of the 8th ACM/IEEE international workshop on Timing issues in the specification and synthesis of digital systems
Parameter variations and impact on circuits and microarchitecture
Proceedings of the 40th annual Design Automation Conference
Speed Binning with Path Delay Test in 150-nm Technology
IEEE Design & Test
Delay Defect Characteristics and Testing Strategies
IEEE Design & Test
Statistical analysis of subthreshold leakage current for VLSI circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
First-order incremental block-based statistical timing analysis
Proceedings of the 41st annual Design Automation Conference
Fast statistical timing analysis handling arbitrary delay correlations
Proceedings of the 41st annual Design Automation Conference
Parametric yield estimation considering leakage variability
Proceedings of the 41st annual Design Automation Conference
Statistical Timing Analysis Considering Spatial Correlations using a Single Pert-Like Traversal
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Full-chip analysis of leakage power under process variations, including spatial correlations
Proceedings of the 42nd annual Design Automation Conference
Proceedings of the 42nd annual Design Automation Conference
High-performance CMOS variability in the 65-nm regime and beyond
IBM Journal of Research and Development - Advanced silicon technology
Statistical timing analysis using bounds and selective enumeration
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Frequency and yield optimization using power gates in power-constrained designs
Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design
Timing yield analysis considering process-induced temperature and supply voltage variations
Microelectronics Journal
Power yield analysis under process and temperature variations
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IBM POWER7+ design for higher frequency at fixed power
IBM Journal of Research and Development
| Hi-index | 0.00 |
Parametric yield loss has become a serious concern in nanometer technologies. In this paper, we propose a methodology to estimate and optimize the parametric yield of a design in the presence of process variations. We discuss the impact of leakage on parametric yield given that leakage causes the parametric yield window to shrink by imposing a two-sided constraint in conjunction with performance targets on the yield window. We present a mathematical framework for yield estimation under process variation for a given power and frequency constraints. The model is validated against Monte Carlo SPICE simulations in a 90-nm CMOS process and is shown to have a typical error of less than 5%. We then demonstrate the importance of optimal supply and threshold voltage selection for yield maximization. Our results show that parametric yield is highly sensitive to supply voltage with only a 5% change in the supply voltage potentially leading to nearly 15% yield degradation. We also investigate the sensitivity of parametric yield to required frequency and power constraints. Finally, we apply the proposed framework to the problem of maximizing the shipping frequency in the presence of given yield and power constraints.