Pentium® Pro Processor Design for Test and Debug
Proceedings of the IEEE International Test Conference
Multiple-output propagation transition fault test
Proceedings of the IEEE International Test Conference 2001
X-Compact: An Efficient Response Compaction Technique for Test Cost Reduction
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Embedded Deterministic Test for Low-Cost Manufacturing Test
ITC '02 Proceedings of the 2002 IEEE International Test Conference
A SmartBIST Variant with Guaranteed Encoding
ATS '01 Proceedings of the 10th Asian Test Symposium
Diagnosis of Sequence-Dependent Chips
VTS '02 Proceedings of the 20th IEEE VLSI Test Symposium
Experimental Results for Slow-Speed Testing
VTS '02 Proceedings of the 20th IEEE VLSI Test Symposium
Validation and Test of Network Processors and ASICs
VTS '02 Proceedings of the 20th IEEE VLSI Test Symposium
Delay Defect Screening using Process Monitor Structures
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
Parametric Yield Analysis and Constrained-Based Supply Voltage Optimization
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Delay defect screening for a 2.16GHz SPARC64 microprocessor
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Parametric yield in FPGAs due to within-die delay variations: a quantitative analysis
Proceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays
Test generation in the presence of timing exceptions and constraints
Proceedings of the 44th annual Design Automation Conference
Parametric yield analysis and optimization in leakage dominated technologies
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Parametric Yield Modeling and Simulations of FPGA Circuits Considering Within-Die Delay Variations
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Exploiting MOEA to automatically geneate test programs for path-delay faults in microprocessors
Evo'08 Proceedings of the 2008 conference on Applications of evolutionary computing
Contributions to the evaluation of ensembles of combinational logic gates
Microelectronics Journal
Effective diagnostic pattern generation strategy for transition-delay faults in full-scan SOCs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Reliability, thermal, and power modeling and optimization
Proceedings of the International Conference on Computer-Aided Design
Journal of Electronic Testing: Theory and Applications
A Non-Enumerative Technique for Measuring Path Correlation in Digital Circuits
Journal of Electronic Testing: Theory and Applications
AC-plus scan methodology for small delay testing and characterization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Editor's note: At-speed testing is undoubtedly critical for designs such as high-performance microprocessors. But how much of a role can structural delay testing play in testing these designs? Are speed problems caused by manufacturing variations or random defects? The authors answer these questions, using their testing experience at Intel.驴Kwang-Ting Cheng, University of California, Santa Barbara