Parametric yield in FPGAs due to within-die delay variations: a quantitative analysis

Authors:
Pete Sedcole;Peter Y. K. Cheung
Affiliations:
Imperial College London, UK;Imperial College London, UK
Venue:
Proceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays
Year:
2007

Citing 11
Cited 8

BIST-based delay path testing in FPGA architectures

Proceedings of the IEEE International Test Conference 2001
Death, taxes and failing chips

Proceedings of the 40th annual Design Automation Conference
Design for Variability in DSM Technologies

ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
BIST-Based Delay-Fault Testing in FPGAs

Journal of Electronic Testing: Theory and Applications
Delay Defect Characteristics and Testing Strategies

IEEE Design & Test
High Quality TPG for Delay Faults in Look-Up Tables of FPGAs

DELTA '04 Proceedings of the Second IEEE International Workshop on Electronic Design, Test and Applications
First-order incremental block-based statistical timing analysis

Proceedings of the 41st annual Design Automation Conference
Parameterized block-based statistical timing analysis with non-gaussian parameters, nonlinear delay functions

Proceedings of the 42nd annual Design Automation Conference
Measurement results of within-die variations on a 90nm LUT array for speed and yield enhancement of reconfigurable devices

ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
FPGA device and architecture evaluation considering process variations

ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
An adaptive FPGA architecture with process variation compensation and reduced leakage

Proceedings of the 43rd annual Design Automation Conference

Trace-based framework for concurrent development of process and FPGA architecture considering process variation and reliability

Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays
Parametric Yield Modeling and Simulations of FPGA Circuits Considering Within-Die Delay Variations

ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Stochastic physical synthesis considering prerouting interconnect uncertainty and process variation for FPGAs

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Yield maximization for system-level task assignment and configuration selection of configurable multiprocessors

CODES+ISSS '08 Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis
FPGA Architecture: Survey and Challenges

Foundations and Trends in Electronic Design Automation
Measuring and modeling variabilityusing low-cost FPGAs

Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
Self-Measurement of Combinatorial Circuit Delays in FPGAs

ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Limit study of energy & delay benefits of component-specific routing

Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays

Quantified Score

Hi-index	0.00

Visualization

Abstract

Variations in the semiconductor fabrication process results in variability in parameters between transistors on the same die, a problem exacerbated by lithographic scaling. The re-configurability of Field-Programmable Gate Arrays presents the opportunity to compensate for within-die delay variability. This paper presents three reconfiguration-based strategies for compensating within-die stochastic delay variability in FPGAs: reconfiguring the entire FPGA, relocating subcircuits within an FPGA, and reconfiguring signal paths within a design. The yield of each strategy is analysed and compared with worst-case design and statistical static timing analysis (SSTA). It is demonstrated that significant im-provements in circuit yield and timing are possible using SSTA alone, and these improvements can be enhanced by employing reconfiguration-based techniques.