Interconnect testing in cluster-based FPGA architectures
Proceedings of the 37th Annual Design Automation Conference
BIST-based test and diagnosis of FPGA logic blocks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
Diagnosis of interconnect faults in cluster-based FPGA architectures
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
On-Line Fault Tolerance for FPGA Interconnect with Roving STARs
DFT '01 Proceedings of the 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems
Built-in self-test of FPGA interconnect
ITC '98 Proceedings of the 1998 IEEE International Test Conference
BIST-based delay path testing in FPGA architectures
Proceedings of the IEEE International Test Conference 2001
A Test Methodology for Interconnect Structures of LUT-based FPGAs
ATS '96 Proceedings of the 5th Asian Test Symposium
Dynamic Fault Tolerance in FPGAs via Partial Reconfiguration
FCCM '00 Proceedings of the 2000 IEEE Symposium on Field-Programmable Custom Computing Machines
On the Necessity of On-line-BIST in Safety-Critical Applications - A Case-Study
FTCS '99 Proceedings of the Twenty-Ninth Annual International Symposium on Fault-Tolerant Computing
Built-in self-test of logic blocks in FPGAs (Finally, a free lunch: BIST without overhead!)
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
BIST-Based Diagnosis of FPGA Interconnect
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Improving On-Line BIST-Based Diagnosis for Roving STARs
IOLTW '00 Proceedings of the 6th IEEE International On-Line Testing Workshop (IOLTW)
EH '01 Proceedings of the The 3rd NASA/DoD Workshop on Evolvable Hardware
IOLTW '01 Proceedings of the Seventh International On-Line Testing Workshop
Using Roving STARs for On-Line Testing and Diagnosis of FPGAs in Fault-Tolerant Applications
ITC '99 Proceedings of the 1999 IEEE International Test Conference
An Automated BIST Architecture for Testing and Diagnosing FPGA Interconnect Faults
Journal of Electronic Testing: Theory and Applications
Parametric yield in FPGAs due to within-die delay variations: a quantitative analysis
Proceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays
Parametric Yield Modeling and Simulations of FPGA Circuits Considering Within-Die Delay Variations
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Self-Measurement of Combinatorial Circuit Delays in FPGAs
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
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We present the first delay-fault testing approach for Field Programmable Gate Arrays (FPGAs), applicable for on-line testing as well as for off-line manufacturing and system-level testing. Our approach is based on Built-In Self-Test (BIST), it is comprehensive, and does not require expensive external test equipment (ATE). We have successfully implemented this BIST approach for delay-fault testing on the Lattice ORCA 2C and Xilinx Spartan FPGAs.