Diagnosing programmable interconnect systems for FPGAs
Proceedings of the 1996 ACM fourth international symposium on Field-programmable gate arrays
Using ILA Testing for BIST in FPGAs
Proceedings of the IEEE International Test Conference on Test and Design Validity
BIST-Based Diagnostics of FPGA Logic Blocks
Proceedings of the IEEE International Test Conference
A Test Methodology for Interconnect Structures of LUT-based FPGAs
ATS '96 Proceedings of the 5th Asian Test Symposium
An approach for testing programmable/configurable field programmable gate arrays
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
Built-in self-test of logic blocks in FPGAs (Finally, a free lunch: BIST without overhead!)
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
Test of RAM-based FPGA: methodology and application to the interconnect
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
Diagnosis of interconnects and FPICs using a structured walking-1 approach
VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
Verification Testing A Pseudoexhaustive Test Technique
IEEE Transactions on Computers
Design of Easily Testable Bit-Sliced Systems
IEEE Transactions on Computers
Testing and diagnosis of interconnects using boundary scan architecture
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
Interconnect testing in cluster-based FPGA architectures
Proceedings of the 37th Annual Design Automation Conference
FPGA test time reduction through a novel interconnect testing scheme
FPGA '02 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays
Using embedded FPGAs for SoC yield improvement
Proceedings of the 39th annual Design Automation Conference
Diagnosis of interconnect faults in cluster-based FPGA architectures
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
A Discussion on Test Pattern Generation for FPGA—Implemented Circuits
Journal of Electronic Testing: Theory and Applications
Analyzing the Test Generation Problem for an Application-Oriented Test of FPGAs
ETW '00 Proceedings of the IEEE European Test Workshop
Enhanced Bist-Based Diagnosis of FPGAs via Boundary Scan Access
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Bridging Fault Extraction from Physical Design Data for Manufacturing Test Development
ITC '00 Proceedings of the 2000 IEEE International Test Conference
NOVEL TECHNIQUE FOR BUILT-IN SELF-TEST OF FPGA INTERCONNECTS
ITC '00 Proceedings of the 2000 IEEE International Test Conference
BIST-Based Detection and Diagnosis of Multiple Faults in FPGAs
ITC '00 Proceedings of the 2000 IEEE International Test Conference
BIST-Based Delay Path Testing in FPGA Architectures
ITC '01 Proceedings of the 2001 IEEE International Test Conference
IS-FPGA: A New Symmetric FPGA Architecture with Implicit SCAN
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Improving On-Line BIST-Based Diagnosis for Roving STARs
IOLTW '00 Proceedings of the 6th IEEE International On-Line Testing Workshop (IOLTW)
BIST-Based Delay-Fault Testing in FPGAs
Journal of Electronic Testing: Theory and Applications
Using Roving STARs for On-Line Testing and Diagnosis of FPGAs in Fault-Tolerant Applications
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Detecting, diagnosing, and tolerating faults in SRAM-based field programmable gate arrays: a survey
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2001 international conference on computer design (ICCD)
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Reconfigurable systems
Application-Specific Bridging Fault Testing of FPGAs
Journal of Electronic Testing: Theory and Applications
Reconfigurable Architecture for Autonomous Self-Repair
IEEE Design & Test
A novel FPGA local interconnect test scheme and automatic TC derivation/generation
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Desing and test of systems on a chip
Delay Fault Testing of Look-Up Tables in SRAM-Based FPGAs
Journal of Electronic Testing: Theory and Applications
An Efficient BIST Architecture for Delay Faults in the Logic Cells of Symmetrical SRAM-Based FPGAs
Journal of Electronic Testing: Theory and Applications
Fault tolerance of switch blocks and switch block arrays in FPGA
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An Automated BIST Architecture for Testing and Diagnosing FPGA Interconnect Faults
Journal of Electronic Testing: Theory and Applications
Application-dependent testing of FPGAs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
Online BIST and BIST-based diagnosis of FPGA logic blocks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Reliability and availability in reconfigurable computing: a basis for a common solution
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A cost-efficient self-configurable BIST technique for testing multiplexer-based FPGA interconnect
Journal of Electronic Testing: Theory and Applications
Fine grain faults diagnosis of FPGA interconnect
Microprocessors & Microsystems
GABES: A genetic algorithm based environment for SEU testing in SRAM-FPGAs
Journal of Systems Architecture: the EUROMICRO Journal
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We introduce the first BIST approach for testingthe programmable routing network in FPGAs. Our methoddetects opens in, and shorts among, wiring segments, and alsofaults affecting the programmable switches that configure theFPGA interconnect. As a result, the BIST technique providescomplete testing of interconnect faults.1