Introduction to VLSI Systems
Truth-Table Verification of an Iterative Logic Array
IEEE Transactions on Computers
A Functional Approach to Testing Bit-Sliced Microprocessors
IEEE Transactions on Computers
Easily Testable Iterative Systems
IEEE Transactions on Computers
AFIPS '65 (Fall, part I) Proceedings of the November 30--December 1, 1965, fall joint computer conference, part I
Testing for faults in combinational cellular logic arrays
FOCS '67 Proceedings of the 8th Annual Symposium on Switching and Automata Theory (SWAT 1967)
Testability Conditions for Bilateral Arrays of Combinational Cells
IEEE Transactions on Computers
Built-in self-test of FPGA interconnect
ITC '98 Proceedings of the 1998 IEEE International Test Conference
BIST-Based Diagnostics of FPGA Logic Blocks
ITC '97 Proceedings of the 1997 IEEE International Test Conference
On the identification of modular test requirements for low cost hierarchical test path construction
Integration, the VLSI Journal
Design of Totally Self-Checking Comparators with an Arbitrary Number of Inputs
IEEE Transactions on Computers
Built-In Testing of One-Dimensional Unilateral Iterative Arrays
IEEE Transactions on Computers
Design-for-testability techniques for CORDIC design
Microelectronics Journal
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Bit-sliced systems are formed by interconnecting identical slices or cells to form a one-dimensional iterative logic array (ILA). This paper presents several design techniques for constructing easily testable bit-sliced systems. Properties of ILA's that simplify their testing are examined. C-testable ILA's, which require a constant number of test patterns independent of the array size, are characterized, and a method for making an arbitrary ILA C-testable is presented. A new testability concept for arrays called I-testability is introduced. I-testability ensures that identical test responses can be obtained from every cell in an ILA, and thus simplifies response verification. I-testable ILA's are characterized, as well as CI-testable arrays, which are simultaneously C- and I-testable. A method of making an arbitrary ILA CI-testable is presented. The application of C- and I-testing to the design of bit-sliced (micro-) computers is investigated. For this purpose a family of easily testable processor slices is described. The design of a self-testing CPU based on I-testing is discussed, and compared with a more conventional self-testing design.