Testability Conditions for Bilateral Arrays of Combinational Cells
IEEE Transactions on Computers
On a new class of C-testable systolic arrays
Integration, the VLSI Journal
Easily Testable Iterative Logic Arrays
IEEE Transactions on Computers
C-testable design techniques for iterative logic arrays
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Cell delay fault testing for iterative logic arrays
Journal of Electronic Testing: Theory and Applications
Sequential Fault Modeling and Test Pattern Generation for CMOS Iterative Logic Arrays
IEEE Transactions on Computers
Effective Built-In Self-Test for Booth Multipliers
IEEE Design & Test
Hardware Efficient Algorithms for Trigonometric Functions
IEEE Transactions on Computers
Testing Iterative Logic Arrays for Sequential Faults with a Constant Number of Patterns
IEEE Transactions on Computers
A C-testable modified Booth's array multiplier
VLSID '95 Proceedings of the 8th International Conference on VLSI Design
High-Throughput CORDIC-Based Geometry Operations for 3D Computer Graphics
IEEE Transactions on Computers
Fault Detection in Iterative Logic Arrays
IEEE Transactions on Computers
The Design of Easily Testable VLSI Array Multipliers
IEEE Transactions on Computers
Built-In Testing of One-Dimensional Unilateral Iterative Arrays
IEEE Transactions on Computers
Physical Versus Logical Fault Models MOS LSI Circuits: Impact on Their Testability
IEEE Transactions on Computers
The Complexity of Fault Detection Problems for Combinational Logic Circuits
IEEE Transactions on Computers
A Testable Design of Iterative Logic Arrays
IEEE Transactions on Computers
Design of Easily Testable Bit-Sliced Systems
IEEE Transactions on Computers
Easily Testable Iterative Systems
IEEE Transactions on Computers
A Scale Factor Correction Scheme for the CORDIC Algorithm
IEEE Transactions on Computers
A unified algorithm for elementary functions
AFIPS '71 (Spring) Proceedings of the May 18-20, 1971, spring joint computer conference
On the detection of delay faults
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
On an improved design approach for C-testable orthogonal iterative arrays
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
C-Testability of Two-Dimensional Iterative Arrays
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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In this paper, we propose two C-testable design-for-testability (DFT) architectures for coordinate rotation digital computer (CORDIC) design. The first design is achieved by using scalable cells. A scalable cell consists of n bit-level cells and has both hardware and bijective scalability. These simple scalable cells establish the relationship between hardware overhead (HO) and number of test patterns (NTP). Both HO and NTP change as n varies. By adjusting the value of n, we can obtain an optimal balance between HO and NTP. Based on these scalable cells, the iterative logic array (ILA) will be still C-testable. For the first proposed design, the HO and NTP for n=2 are 5.37% and 74, respectively. The second one is achieved by the reorganized test sequences, where the HO and NTP are only 3.15% and 18, respectively. The first design can be connected into a non-homogenous ILA for saving lot of test pins and built-in self-test (BIST) area; in the second one, the special properties of the sequences reduce HO/NTP significantly.