A logic design structure for LSI testability
DAC '77 Proceedings of the 14th Design Automation Conference
Syndrome-Testable Design of Combinational Circuits
IEEE Transactions on Computers
Truth-Table Verification of an Iterative Logic Array
IEEE Transactions on Computers
A Functional Approach to Testing Bit-Sliced Microprocessors
IEEE Transactions on Computers
Design of Easily Testable Bit-Sliced Systems
IEEE Transactions on Computers
Easily Testable Iterative Systems
IEEE Transactions on Computers
An effective BIST design for PLA
ATS '95 Proceedings of the 4th Asian Test Symposium
Design-for-testability techniques for CORDIC design
Microelectronics Journal
| Hi-index | 14.98 |
It has been shown in the literature that C-testable iterative arrays have very simple test structures, independent of the length of the arrays. We show in this work that all C-testable arrays are also pI-testable, which is a property yielding, in many cases, rather simple built-in-testing structures, both for the test generator and for the response verifier.