Introduction to VLSI Systems
Microprogrammable microprocessor survey
ACM SIGMICRO Newsletter
Microprogrammable microprocessor survey
ACM SIGMICRO Newsletter
A Module-Level Testing Approach for Combinational Networks
IEEE Transactions on Computers
Truth-Table Verification of an Iterative Logic Array
IEEE Transactions on Computers
Easily Testable Iterative Systems
IEEE Transactions on Computers
Testability Conditions for Bilateral Arrays of Combinational Cells
IEEE Transactions on Computers
Functional Test Generation for Digital Circuits Described Using Binary Decision Diagrams
IEEE Transactions on Computers - The MIT Press scientific computation series
ATS '95 Proceedings of the 4th Asian Test Symposium
The Design of Easily Testable VLSI Array Multipliers
IEEE Transactions on Computers
Built-In Testing of One-Dimensional Unilateral Iterative Arrays
IEEE Transactions on Computers
Functional Testing of Microprocessors
IEEE Transactions on Computers
Design of Easily Testable Bit-Sliced Systems
IEEE Transactions on Computers
Software testing techniques for universal building blocks of multimicrosystems
AFIPS '82 Proceedings of the June 7-10, 1982, national computer conference
CADOC: a system for computed aided functional test
ITC'84 Proceedings of the 1984 international test conference on The three faces of test: design, characterization, production
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Bit-sliced microprocessors are representative of an important class of LSI components that can be interconnected in a regular way to construct many useful types of digital systems. This paper develops an analytic test generation methodology for bit-sliced systems. A formal model C for a 1-bit bit-sliced microprocessor is defined which has the main features of many commercially available microprocessors. Using a functional fault model instead of the usual stuck-line fault model, a technique is presented for deriving a complete and near-minimal sequence of tests for C. The basic cell C is extended to form two more general cells Ck and Ck. n. Ck is a k-bit version of C, while Ck, n is Ck with an n 脳 k-bit scratchpad RAM. The internal structure of C4,16 closely resembles that of the AMD 2901 processor slice. Test sequences for these cells are derived in much the same way as for C. It is shown that the test sequence for a single cell (C, Ck, or Ck, n) can easily be extended to a test sequence for an array of N identical cells with no increase in the number of tests required. It is observed that for test generation purposes, bit-sliced microprocessors can be viewed as C-testable iterative logic arrays, which require a constant number of test patterns independent of array size. Some new results on test generation for C-testable systems are presented, as well as a method for modifying iterative logic arrays to make them C-testable.