Computer Arithmetic: Principles, Architecture and Design
Computer Arithmetic: Principles, Architecture and Design
Introduction to VLSI Systems
Design for Testability A Survey
IEEE Transactions on Computers
A Functional Approach to Testing Bit-Sliced Microprocessors
IEEE Transactions on Computers
Easily Testable Iterative Systems
IEEE Transactions on Computers
Testing for faults in combinational cellular logic arrays
FOCS '67 Proceedings of the 8th Annual Symposium on Switching and Automata Theory (SWAT 1967)
A minimum test set for multiple fault detection on ripple carry adders
IEEE Transactions on Computers
High-coverage ATPG for datapath circuits with unimplemented blocks
ITC '98 Proceedings of the 1998 IEEE International Test Conference
An effective BIST design for PLA
ATS '95 Proceedings of the 4th Asian Test Symposium
A C-testable modified Booth's array multiplier
VLSID '95 Proceedings of the 8th International Conference on VLSI Design
8.1 Robustly Testable Array Multipliers under Realistic Sequential Cell Fault Model
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Design-for-testability techniques for CORDIC design
Microelectronics Journal
| Hi-index | 14.98 |
Array multipliers are well suited for VLSI implementation because of the regularity in their iterative structure. However, most VLSI circuits are difficult to test. This correspondence shows that, with appropriate cell design, array multipliers can be designed to be very easily testable. An array multiplier is called C-testable if all its adder cells can be exhaustively tested while requiring only a constant number of test patterns. The testability of two well-known array multiplier structures is studied in detail. The conventional design of the carry-save array multiplier is modified. The modified design is shown to be C-testable and requires only 16 test patterns. Similar results are obtained for the Baugh-Wooley two's complement array multiplier. A modified design of the Baugh-Wooley array multiplier is shown to be C-testable and requires 55 test patterns. The C-testability of two other array multipliers, namely the carry-propagate and the TRW designs, is also presented.