Fault Detection in Iterative Logic Arrays
IEEE Transactions on Computers
The Design of Easily Testable VLSI Array Multipliers
IEEE Transactions on Computers
Truth-Table Verification of an Iterative Logic Array
IEEE Transactions on Computers
Multiple Fault Detection in Arrays of Combinational Cells
IEEE Transactions on Computers
A Testable Design of Iterative Logic Arrays
IEEE Transactions on Computers
Design of Testable Structures Defined by Simple Loops
IEEE Transactions on Computers
Easily Testable Iterative Systems
IEEE Transactions on Computers
Testing for faults in combinational cellular logic arrays
FOCS '67 Proceedings of the 8th Annual Symposium on Switching and Automata Theory (SWAT 1967)
Easily Testable Iterative Logic Arrays
IEEE Transactions on Computers
Detection of Multiple Faults in Two-Dimensional ILAs
IEEE Transactions on Computers
| Hi-index | 14.99 |
Previous papers have shown that a ripple carry adder composed of several full adder cells can be completely tested by a minimum test set of size 8 independent of the number of cells in the ripple carry adder under single faulty cell assumption. The fault model assumed is that faults in a cell can change the cell behavior in any arbitrary way, as long as the cell remains a combinational circuit. In this paper, we assume that any number of cells can be faulty at any time. A minimum test set of size 11 which can detect arbitrary length ripple carry adders under this fault model is presented. For general (N, p) adders in which each cell is a p-bit adder, a minimum test set of size 3 × 22P − 1 is also presented.