Testability Conditions for Bilateral Arrays of Combinational Cells
IEEE Transactions on Computers
Partitioning circuits for inproved testability
Proceedings of the fourth MIT conference on Advanced research in VLSI
A minimum test set for multiple fault detection on ripple carry adders
IEEE Transactions on Computers
Graph Algorithms
On the Testability of One-Dimensional ILAs for Multiple Sequential Faults
IEEE Transactions on Computers
A multi level testability assistant for VLSI design
EURO-DAC '92 Proceedings of the conference on European design automation
Detection of Multiple Faults in Two-Dimensional ILAs
IEEE Transactions on Computers
Testability of Convergent Tree Circuits
IEEE Transactions on Computers
Testability Properties of Divergent Trees
Journal of Electronic Testing: Theory and Applications
Efficient FFT network testing and diagnosis schemes
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Testing Iterative Logic Arrays for Sequential Faults with a Constant Number of Patterns
IEEE Transactions on Computers
Easily Testable Cellular Carry Lookahead Adders
Journal of Electronic Testing: Theory and Applications
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Testable design techniques for variable block size motion estimator used in H.264/AVC
AIC'06 Proceedings of the 6th WSEAS International Conference on Applied Informatics and Communications
Efficient built-in self-test techniques for sequential fault testing of iterative logic arrays
AIC'06 Proceedings of the 6th WSEAS International Conference on Applied Informatics and Communications
Detecting Multiple Faults in One-Dimensional Arrays of Reversible QCA Gates
Journal of Electronic Testing: Theory and Applications
Design-for-testability techniques for CORDIC design
Microelectronics Journal
Design-for-testability and fault-tolerant techniques for FFT processors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Testable design techniques for variable block size motion estimator used in H.264/AVC
IMCAS'06 Proceedings of the 5th WSEAS international conference on Instrumentation, measurement, circuits and systems
Efficient built-in self-test techniques for sequential fault testing of iterative logic arrays
IMCAS'06 Proceedings of the 5th WSEAS international conference on Instrumentation, measurement, circuits and systems
ALADIN: a multilevel testability analyzer for VLSI system design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Iterative logic arrays (ILAs) are studied with respect to two testing problems. First, a variety of conditions is presented. Meeting these conditions guarantees an upper bound on the size of the test set for the ILA under consideration. Second, techniques for designing optimally testable ILAs are presented. The arrays treated are, in some cases, more general than those that have been reported by other researchers: they include multidimensional and inhomogeneous arrays. Octagonally connected arrays and bilateral arrays are also discussed. The results indicate that the characteristics of the individual cell functions (e.g. whether they are bijective) are a good guide to the test complexity of the overall array. Matrix multiplication, as an example, is shown to have several different optimally testable implementations. The results are useful for combinational and pipelined arrays and for certain systolic arrays.