Easily Testable Iterative Logic Arrays
IEEE Transactions on Computers
VLSID '05 Proceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design
Testing Reversible 1D Arrays for Molecular QCA
DFT '06 Proceedings of the 21st IEEE International Symposium on on Defect and Fault-Tolerance in VLSI Systems
An Information Theoretic Approach to Digital Fault Testing
IEEE Transactions on Computers
Easily Testable Iterative Systems
IEEE Transactions on Computers
Testing of quantum cellular automata
IEEE Transactions on Nanotechnology
Fault testing for reversible circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Design of efficient reversible logic-based binary and BCD adder circuits
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Mach-zehnder interferometer based design of all optical reversible binary adder
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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Reversible logic design is a well-known paradigm in digital computation. In this paper, quantum-dot cellular automata (QCA) is investigated for testable implementations of reversible logic in array systems. Testability of 1D arrays consisting of reversible QCA gates is investigated for multiple faulty modules. It has been shown that fault masking is possible in the presence of multiple faults without additional lines for controllability and observability. A technique for achieving C-testability of a 1D array is introduced by adding lines for observability. By adding lines for controllability, as well as observability, the array may be fully tested with a smaller number of test patterns. Different cases of arrays made of QCA reversible gates are presented to illustrate the applicability of the proposed testing method.