Quantum computation and quantum information
Quantum computation and quantum information
A reversible carry-look-ahead adder using control gates
Integration, the VLSI Journal
Decimal Floating-Point: Algorism for Computers
ARITH '03 Proceedings of the 16th IEEE Symposium on Computer Arithmetic (ARITH-16'03)
Efficient Adder Circuits Based on a Conservative Reversible Logic Gate
ISVLSI '02 Proceedings of the IEEE Computer Society Annual Symposium on VLSI
Approaching the Physical Limits of Computing
ISMVL '05 Proceedings of the 35th International Symposium on Multiple-Valued Logic
Design of a compact reversible binary coded decimal adder circuit
Journal of Systems Architecture: the EUROMICRO Journal
Data structures and algorithms for simplifying reversible circuits
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Quantum ternary parallel adder/subtractor with partially-look-ahead carry
Journal of Systems Architecture: the EUROMICRO Journal
Arithmetic on a distributed-memory quantum multicomputer
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Synthesis of reversible sequential elements
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Bi-Directional Synthesis of 4-Bit Reversible Circuits
The Computer Journal
Reversible Gates and Testability of One Dimensional Arrays of Molecular QCA
Journal of Electronic Testing: Theory and Applications
Exact Synthesis of Elementary Quantum Gate Circuits for Reversible Functions with Don't Cares
ISMVL '08 Proceedings of the 38th International Symposium on Multiple Valued Logic
Optimized reversible binary-coded decimal adders
Journal of Systems Architecture: the EUROMICRO Journal
An Introduction to Reversible Latches
The Computer Journal
Efficient approaches for designing reversible Binary Coded Decimal adders
Microelectronics Journal
Detecting Multiple Faults in One-Dimensional Arrays of Reversible QCA Gates
Journal of Electronic Testing: Theory and Applications
On figures of merit in reversible and quantum logic designs
Quantum Information Processing
Design of Efficient Reversible Binary Subtractors Based on a New Reversible Gate
ISVLSI '09 Proceedings of the 2009 IEEE Computer Society Annual Symposium on VLSI
Exact multiple-control toffoli network synthesis with SAT techniques
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Computer Arithmetic: Algorithms and Hardware Designs
Computer Arithmetic: Algorithms and Hardware Designs
Reducing the number of lines in reversible circuits
Proceedings of the 47th Design Automation Conference
A survey of hardware designs for decimal arithmetic
IBM Journal of Research and Development
Design of reversible sequential circuits optimizing quantum cost, delay, and garbage outputs
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Quantum addition circuits and unbounded fan-out
Quantum Information & Computation
A linear-size quantum circuit for addition with no ancillary qubits
Quantum Information & Computation
Reversible Logic-Based Concurrently Testable Latches for Molecular QCA
IEEE Transactions on Nanotechnology
Synthesis of reversible logic circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Reversible cascades with minimal garbage
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An Algorithm for Synthesis of Reversible Logic Circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
RMDDS: Reed-muller decision diagram synthesis of reversible logic circuits
ACM Journal on Emerging Technologies in Computing Systems (JETC)
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Reversible logic is gaining significance in the context of emerging technologies such as quantum computing since reversible circuits do not lose information during computation and there is one-to-one mapping between the inputs and outputs. In this work, we present a class of new designs for reversible binary and BCD adder circuits. The proposed designs are primarily optimized for the number of ancilla inputs and the number of garbage outputs and are designed for possible best values for the quantum cost and delay. In reversible circuits, in addition to the primary inputs, some constant input bits are used to realize different logic functions which are referred to as ancilla inputs and are overheads that need to be reduced. Further, the garbage outputs which do not contribute to any useful computations but are needed to maintain reversibility are also overheads that need to be reduced in reversible designs. First, we propose two new designs for the reversible ripple carry adder: (i) one with no input carry c0 and no ancilla input bits, and (ii) one with input carry c0 and no ancilla input bits. The proposed reversible ripple carry adder designs with no ancilla input bits have less quantum cost and logic depth (delay) compared to their existing counterparts in the literature. In these designs, the quantum cost and delay are reduced by deriving designs based on the reversible Peres gate and the TR gate. Next, four new designs for the reversible BCD adder are presented based on the following two approaches: (i) the addition is performed in binary mode and correction is applied to convert to BCD when required through detection and correction, and (ii) the addition is performed in binary mode and the result is always converted using a binary to BCD converter. The proposed reversible binary and BCD adders can be applied in a wide variety of digital signal processing applications and constitute important design components of reversible computing.