Digital systems: principles and applications (5th ed.)
Digital systems: principles and applications (5th ed.)
Reversible Logic Synthesis for Minimization of Full-Adder Circuit
DSD '03 Proceedings of the Euromicro Symposium on Digital Systems Design
Synthesis of Full-Adder Circuit Using Reversible Logic
VLSID '04 Proceedings of the 17th International Conference on VLSI Design
A Synthesis Method for MVL Reversible Logic
ISMVL '04 Proceedings of the 34th International Symposium on Multiple-Valued Logic
Reversible cascades with minimal garbage
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A reversible programming language and its invertible self-interpreter
Proceedings of the 2007 ACM SIGPLAN symposium on Partial evaluation and semantics-based program manipulation
Optimized reversible binary-coded decimal adders
Journal of Systems Architecture: the EUROMICRO Journal
A BCD-based architecture for fast coordinate rotation
Journal of Systems Architecture: the EUROMICRO Journal
Efficient approaches for designing reversible Binary Coded Decimal adders
Microelectronics Journal
Efficient Reversible Logic Design of BCD Subtractors
Transactions on Computational Science III
Comment on “Efficient approaches for designing reversible Binary Coded Decimal adders”
Microelectronics Journal
Transistor realization of reversible "ZS" series gates and reversible array multiplier
Microelectronics Journal
Novel design of a fast reversible Wallace sign multiplier circuit in nanotechnology
Microelectronics Journal
On the compact designs of low power reversible decoders and sequential circuits
VDAT'12 Proceedings of the 16th international conference on Progress in VLSI Design and Test
Design of efficient reversible logic-based binary and BCD adder circuits
ACM Journal on Emerging Technologies in Computing Systems (JETC)
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Reversible logic is an emerging research area and getting remarkable interests over the past few years. Interest is sparked in reversible logic by its applications in several technologies, such as quantum, optical, thermodynamics and adiabatic CMOS. This paper represents a synthesis method to realize reversible binary coded decimal adder circuit. Firstly, a reversible full-adder circuit has been proposed that shows the improvement over the two existing circuits. A lower bound is also proposed for the reversible full-adder circuit on the number of garbage outputs (bits needed for reversibility, but not required for the output of the circuit). After that, a final improvement is presented for the reversible full-adder circuit. Finally, a new reversible circuit has been proposed, namely reversible binary coded decimal (BCD) adder, which is the first ever proposed in reversible logic synthesis. In the way to propose reversible BCD adder, a reversible n-bits parallel adder circuit is also shown. Lower bounds for the reversible BCD adder in terms of number of garbage outputs and number of reversible gates are also shown. Delay has also been calculated for each circuit.