Proceedings of the 7th Colloquium on Automata, Languages and Programming
Reversible computing: from mathematical group theory to electronical circuit experiment
Proceedings of the 2nd conference on Computing frontiers
Novel BCD Adders and Their Reversible Logic Implementation for IEEE 754r Format
VLSID '06 Proceedings of the 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design
Design of a compact reversible binary coded decimal adder circuit
Journal of Systems Architecture: the EUROMICRO Journal
Irreversibility and heat generation in the computing process
IBM Journal of Research and Development
Synthesis of fredkin-toffoli reversible networks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
The new BCD subtractor and its reversible logic implementation
ACSAC'06 Proceedings of the 11th Asia-Pacific conference on Advances in Computer Systems Architecture
Synthesis of reversible logic circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Reversible cascades with minimal garbage
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Parallel Optimization of a Reversible (Quantum) Ripple-Carry Adder
UC '08 Proceedings of the 7th international conference on Unconventional Computing
Design of reversible sequential circuits optimizing quantum cost, delay, and garbage outputs
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Improving ESOP-based synthesis of reversible logic using evolutionary algorithms
EvoApplications'11 Proceedings of the 2011 international conference on Applications of evolutionary computation - Volume Part II
Reversible circuits: recent accomplishments and future challenges for an emerging technology
VDAT'12 Proceedings of the 16th international conference on Progress in VLSI Design and Test
Design of efficient reversible logic-based binary and BCD adder circuits
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Trading off circuit lines and gate costs in the synthesis of reversible logic
Integration, the VLSI Journal
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Babu and Chowdhury [H.M.H. Babu, A.R. Chowdhury, Design of a compact reversible binary coded decimal adder circuit, Journal of Systems Architecture 52 (5) (2006) 272-282] recently proposed, in this journal, a reversible adder for binary-coded decimals. This paper corrects and optimizes their design. The optimized 1-decimal BCD full-adder, a 13x13 reversible logic circuit, is faster, and has lower circuit cost and less garbage bits. It can be used to build a fast reversible m-decimal BCD full-adder that has a delay of only m+17 low-power reversible CMOS gates. For a 32-decimal (128-bit) BCD addition, the circuit delay of 49 gates is significantly lower than is the number of bits used for the BCD representation. A complete set of reversible half- and full-adders for n-bit binary numbers and m-decimal BCD numbers is presented. The results show that special-purpose design pays off in reversible logic design by drastically reducing the number of garbage bits. Specialized designs benefit from support by reversible logic synthesis. All circuit components required for optimizing the original design could also be synthesized successfully by an implementation of an existing synthesis algorithm.