The new BCD subtractor and its reversible logic implementation

Authors:
Himanshu Thapliyal;M. B Srinivas
Affiliations:
International Institute of Information Technology, Center for VLSI and Embedded System Technologies, Hyderabad, India;International Institute of Information Technology, Center for VLSI and Embedded System Technologies, Hyderabad, India
Venue:
ACSAC'06 Proceedings of the 11th Asia-Pacific conference on Advances in Computer Systems Architecture
Year:
2006

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Abstract

IEEE 754r is the ongoing revision to the IEEE 754 floating point standard and a major enhancement to the standard is the addition of decimal format. Thus in this paper we propose a novel BCD subtractor called carry skip BCD subtractor. We also propose the reversible logic implementation of the proposed carry skip BCD subtractor. Reversible logic is emerging as a promising computing paradigm having its applications in low power CMOS, quantum computing, nanotechnology, and optical computing. It is not possible to realize quantum computing without reversible logic. It is being tried to design the BCD subtractor optimal in terms of number of reversible gates and garbage outputs.