High-Speed Multioperand Decimal Adders
IEEE Transactions on Computers
Fast decimal floating-point division
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Decimal floating-point in z9: an implementation and testing perspective
IBM Journal of Research and Development
A Radix-10 Digit-Recurrence Division Unit: Algorithm and Architecture
IEEE Transactions on Computers
A Decimal Floating-Point Divider Using Newton---Raphson Iteration
Journal of VLSI Signal Processing Systems
Multioperand Parallel Decimal Adder: A Mixed Binary and BCD Approach
IEEE Transactions on Computers
IBM POWER6 accelerators: VMX and DFU
IBM Journal of Research and Development
A BCD-based architecture for fast coordinate rotation
Journal of Systems Architecture: the EUROMICRO Journal
Efficient Reversible Logic Design of BCD Subtractors
Transactions on Computational Science III
A fully redundant decimal adder and its application in parallel decimal multipliers
Microelectronics Journal
Fully redundant decimal addition and subtraction using stored-unibit encoding
Integration, the VLSI Journal
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
A combined decimal and binary floating-point divider
Asilomar'09 Proceedings of the 43rd Asilomar conference on Signals, systems and computers
Design and evaluation of decimal array multipliers
Asilomar'09 Proceedings of the 43rd Asilomar conference on Signals, systems and computers
Decimal floating-point support on the IBM system z10 processor
IBM Journal of Research and Development
A survey of hardware designs for decimal arithmetic
IBM Journal of Research and Development
High-speed FPGA 10's complement adders-subtractors
International Journal of Reconfigurable Computing - Special issue on selected papers from spl 2009 programmable logic and applications
Error-free algorithm and architecture of radix-10 logarithmic converter
Computers and Electrical Engineering
Function approximation on decimal operands
Digital Signal Processing
International Journal of Reconfigurable Computing - Special issue on selected papers from ReconFig 2009 International conference on reconfigurable computing and FPGAs (ReconFig 2009)
The new BCD subtractor and its reversible logic implementation
ACSAC'06 Proceedings of the 11th Asia-Pacific conference on Advances in Computer Systems Architecture
A study of decimal left shifters for binary numbers
Information and Computation
An iterative method for improving decimal calculations on computers
Mathematical and Computer Modelling: An International Journal
Design of efficient reversible logic-based binary and BCD adder circuits
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Area Efficient Sequential Decimal Fixed-point Multiplier
Journal of Signal Processing Systems
| Hi-index | 0.01 |
Decimal arithmetic is the norm in human calculations, and human-centric applications must use a decimal floating-point arithmetic to achieve the same results.Initial benchmarks indicate that some applications spend 50% to 90% of their time in decimal processing, because software decimal arithmetic suffers a 100脳 to 1000脳 performance penalty over hardware. The need for decimal floating-point in hardware is urgent.Existing designs, however, either fail to conform to modern standards or are incompatible with the established rules of decimal arithmetic. This paper introduces a new approach to decimal floating-point which not only provides the strict results which are necessary for commercial applications but also meets the constraints and requirements of the IEEE 854 standard.A hardware implementation of this arithmetic is in development, and it is expected that this will significantly accelerate a wide variety of applications.