Fast decimal floating-point division

Authors:
Hooman Nikmehr;Braden Phillips;Cheng-Chew Lim
Affiliations:
Department of Computer Engineering, Bu Ali Sina University, Hamedan, Iran;School of Electrical and Electronic Engineering, University of Adelaide, Adelaide, SA, Australia;School of Electrical and Electronic Engineering, University of Adelaide, Adelaide, SA, Australia
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2006

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Abstract

A new implementation for decimal floating-point (DFP) division is introduced. The algorithm is based on high-radix SRT division with the recurrence in a new decimal signed-digit format. Quotient digits are selected using comparison multiples, where the magnitude of the quotient digit is calculated by comparing the truncated partial remainder with limited precision multiples of the divisor. The sign is determined concurrently by investigating the polarity of the truncated partial remainder. A timing evaluation using a logic synthesis shows a significant decrease in the division execution time in contrast with one of the fastest DFP dividers reported in the open literature.