Radix-4 Square Rot Without Initial PLA
IEEE Transactions on Computers
1995 high level synthesis design repository
ISSS '95 Proceedings of the 8th international symposium on System synthesis
Unified Mixed Radix 2-4 Redundant CORDIC Processor
IEEE Transactions on Computers
Area and performance tradeoffs in floating-point divide and square-root implementations
ACM Computing Surveys (CSUR)
Design Issues in Division and Other Floating-Point Operations
IEEE Transactions on Computers
ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
Division Algorithms and Implementations
IEEE Transactions on Computers
High Performance Rotation Architectures Based on the Radix-4 CORDIC Algorithm
IEEE Transactions on Computers
Power-delay tradeoffs for radix-4 and radix-8 dividers
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Radix-4 Vectoring CORDIC Algorithm and Architectures
Journal of VLSI Signal Processing Systems - Special issue on application specific systems, architectures and processors
A Mechanically Checked Proof of the AMD5K86TM Floating-Point Division Program
IEEE Transactions on Computers
IEEE Transactions on Computers
A High-Speed Reduced-Size Adder Under Left-to-Right Input Arrival
IEEE Transactions on Computers
Very High Radix Square Root with Prescaling and Rounding and a Combined Division/Square Root Unit
IEEE Transactions on Computers
IEEE Transactions on Computers - Special issue on computer arithmetic
Improving Goldschmidt Division, Square Root, and Square Root Reciprocal
IEEE Transactions on Computers - Special issue on computer arithmetic
A VLSI Algorithm for Computing the Euclidean Norm of a 3D Vector
IEEE Transactions on Computers
Boosting Very-High Radix Division with Prescaling and Selection by Rounding
IEEE Transactions on Computers
Journal of VLSI Signal Processing Systems
Very-High Radix Division with Prescaling and Selection by Rounding
IEEE Transactions on Computers
High-Radix Division and Square-Root with Speculation
IEEE Transactions on Computers
High-Speed Double-Precision Computation of Reciprocal, Division, Square Root and Inverse Square Root
IEEE Transactions on Computers
Divider Circuit Verification with Model Checking and Theorem Proving
TPHOLs '00 Proceedings of the 13th International Conference on Theorem Proving in Higher Order Logics
Proof Engineering in the Large: Formal Verification of Pentium® 4 Floating-Point Divider
CHARME '01 Proceedings of the 11th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Small Multiplier-Based Multiplication and Division Operators for Virtex-II Devices
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
An FPGA-Based Fan Beam Image Reconstruction Module
FCCM '99 Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Implementation of Near Shannon Limit Error-Correcting Codes Using Reconfigurable Hardware
FCCM '00 Proceedings of the 2000 IEEE Symposium on Field-Programmable Custom Computing Machines
Svoboda-Tung division with no compensation
VLSID '95 Proceedings of the 8th International Conference on VLSI Design
Radix-4 Reciprocal Square-Root and Its Combination with Division and Square Root
IEEE Transactions on Computers
Pipelined area-efficient digit serial divider
Signal Processing
IEEE Transactions on Computers
Design of a cycle-efficient 64-b/32-b integer divisor using a table-sharing algorithm
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Synthesis and verification
Algorithm and Architecture for Logarithm, Exponential, and Powering Computation
IEEE Transactions on Computers
The IBM eServer z990 floating-point unit
IBM Journal of Research and Development
Digit Selection for SRT Division and Square Root
IEEE Transactions on Computers
High-Speed Function Approximation Using a Minimax Quadratic Interpolator
IEEE Transactions on Computers
High-Radix Logarithm with Selection by Rounding: Algorithm and Implementation
Journal of VLSI Signal Processing Systems
Digit-Recurrence Dividers with Reduced Logical Depth
IEEE Transactions on Computers
Reciprocal and Reciprocal Square Root Units with Operand Modification and Multiplication
Journal of VLSI Signal Processing Systems
Fast decimal floating-point division
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A Radix-10 Digit-Recurrence Division Unit: Algorithm and Architecture
IEEE Transactions on Computers
Interactive presentation: Radix 4 SRT division with quotient prediction and operand scaling
Proceedings of the conference on Design, automation and test in Europe
Calculation scheme based on a weighted primitive: application to image processing transforms
EURASIP Journal on Applied Signal Processing
Complex Square Root with Operand Prescaling
Journal of VLSI Signal Processing Systems
The Negative Two's Complement Number System
Journal of VLSI Signal Processing Systems
A Tool for Unbiased Comparison between Logarithmic and Floating-point Arithmetic
Journal of VLSI Signal Processing Systems
A pipelined divider with a small lookup table
IMCAS'07 Proceedings of the 6th WSEAS International Conference on Instrumentation, Measurement, Circuits and Systems
Efficient implementation of constant coefficient division under quantization constraints
ICC'05 Proceedings of the 9th International Conference on Circuits
Parametric architecture for function calculation improvement
ARCS'07 Proceedings of the 20th international conference on Architecture of computing systems
A novel implementation of radix-4 floating-point division/square-root using comparison multiples
Computers and Electrical Engineering
Simplifying the rounding for Newton-Raphson algorithm with parallel remainder
Asilomar'09 Proceedings of the 43rd Asilomar conference on Signals, systems and computers
A combined decimal and binary floating-point divider
Asilomar'09 Proceedings of the 43rd Asilomar conference on Signals, systems and computers
Asilomar'09 Proceedings of the 43rd Asilomar conference on Signals, systems and computers
A new compact SD2 positive integer triangular array division circuit
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Minimizing the complexity of SRT tables
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Hierarchical segmentation for hardware function evaluation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Improvement of image transform calculation based on a weighted primitive
ICIAR'06 Proceedings of the Third international conference on Image Analysis and Recognition - Volume Part I
The setup for triangle rasterization
EGGH'96 Proceedings of the Eleventh Eurographics conference on Graphics Hardware
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