On-the-fly conversion of redundant into conventional representations
IEEE Transactions on Computers
Computer arithmetic algorithms
Computer arithmetic algorithms
Division and Square Root: Digit-Recurrence Algorithms and Implementations
Division and Square Root: Digit-Recurrence Algorithms and Implementations
SRT Division Architectures and Implementations
ARITH '97 Proceedings of the 13th Symposium on Computer Arithmetic (ARITH '97)
High-Radix Parallel VLSI Dividers without Using Quotient Digit Selection Tables
ISMVL '00 Proceedings of the 30th IEEE International Symposium on Multiple-Valued Logic
Design of a cycle-efficient 64-b/32-b integer divisor using a table-sharing algorithm
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A Hardware Algorithm for Integer Division
ARITH '05 Proceedings of the 17th IEEE Symposium on Computer Arithmetic
A Hardware Algorithm for Integer Division Using the SD2 Representation
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
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Division is the highest latency arithmetic operation in present digital architectures and high-performance computing systems; as such drives the demand for efficient hardware division units. Accordingly, this paper proposes a novel architecture for a nonrestoring divisor based on the radix-2 signed-digit (SD2) representation. This notation has been chosen to achieve fast computation, as proposed by Avizienis (IEEE Transactions on Electronic Computers, vol. EC-10, no. 3, pp. 389-400, Sep. 1961), but the architecture presented in this paper, due to its structure and the definition of the cell implementing its architecture, saves area as well. The proposed divisor architecture is able to achieve a delay of order n, similar to the solution presented by Takagi et al. (IEICE Transactions on Fundamentals of Electronics, Communications, and Computer Sciences, E89-A, no. 10, pp. 2874-2881, 2006) being considered as the state of the art, instead of other solutions that give O(n2) growth. This is in line with the fact that even if our carry-chains have a less impact on the circuit the basic cell is larger compared to the one proposed by Takagi et al. Our cells are larger that those proposed in literature, considering them as single circuit, but considering the overall structure there is a saving of some 40% in the number of gates and a gain of 55% in terms of power saving when compared with the state of the art.