The Mathematics of the Pentium Division Bug
SIAM Review
Computer Arithmetic: Principles, Architecture and Design
Computer Arithmetic: Principles, Architecture and Design
Division and Square Root: Digit-Recurrence Algorithms and Implementations
Division and Square Root: Digit-Recurrence Algorithms and Implementations
Design of a Radix 4 Division Unit with Simple Selection Table
IEEE Transactions on Computers
High-Radix Parallel VLSI Dividers without Using Quotient Digit Selection Tables
ISMVL '00 Proceedings of the 30th IEEE International Symposium on Multiple-Valued Logic
A new compact SD2 positive integer triangular array division circuit
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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In new generations of microprocessors, the superscalar architecture is widely adopted to increase the number of instructions executed in one cycle. The division instruction among all of the instructions needs more cycles than the rest, e.g., addition and multiplication. It then makes division instruction an important cycles-per-instruction figure for modern microprocessors. In this paper, a radix-16/8/4/2 divisor is proposed, which uses a variety of techniques, including operand scaling, table partitioning, and, particularly, table sharing, to increase performance without the cost of increasing complexity. A physical chip using the proposed method is implemented by 0.35-µm single poly four metal (1P4M) CMOS technology. The testing measurement shows that the chip can execute signed 64-b/32-b integer division between 3-13 cycles with a 80-MHz operating clock.