IEEE Transactions on Computers
On-Line Algorithms for Division and Multiplication
IEEE Transactions on Computers
Higher-Radix Division Using Estimates of the Divisor and Partial Remainders
IEEE Transactions on Computers
Redundant and On-Line CORDIC: Application to Matrix Triangularization and SVD
IEEE Transactions on Computers
Fast Multiplication Without Carry-Propagate Addition
IEEE Transactions on Computers
Radix-4 Square Rot Without Initial PLA
IEEE Transactions on Computers
IEEE Transactions on Computers
Higher Radix Square Root with Prescaling
IEEE Transactions on Computers - Special issue on computer arithmetic
Constant-Factor Redundant CORDIC for Angle Calculation and Rotation
IEEE Transactions on Computers - Special issue on computer arithmetic
Hardware Implementation of Montgomery's Modular Multiplication Algorithm
IEEE Transactions on Computers
Carry-Save Multiplication Schemes Without Final Addition
IEEE Transactions on Computers
Radix 2 Division with Over-Redundant Quotient Selection
IEEE Transactions on Computers
Division Algorithms and Implementations
IEEE Transactions on Computers
Parallel Compensation of Scale Factor for the CORDIC Algorithm
Journal of VLSI Signal Processing Systems
IEEE Transactions on Computers
A High-Speed Reduced-Size Adder Under Left-to-Right Input Arrival
IEEE Transactions on Computers
Journal of VLSI Signal Processing Systems
A Radix 2 Shared Division/Square Root Algorithm and its VLSI Architecture
Journal of VLSI Signal Processing Systems
Digit Pipelined Arithmetic for 3-D Massively Parallel Optoelectronic Circuits
The Journal of Supercomputing
On-the-Fly Algorithms and Sequential Machines
IEEE Transactions on Computers
A VLSI Algorithm for Computing the Euclidean Norm of a 3D Vector
IEEE Transactions on Computers
Journal of VLSI Signal Processing Systems
A FPGA-based Library for On-Line Signal Processing
Journal of VLSI Signal Processing Systems
Evaluation of CORDIC Algorithms for FPGA Design
Journal of VLSI Signal Processing Systems
Simple Radix-4 Division with Operands Scaling
IEEE Transactions on Computers
On-the-Fly Rounding (Computing Arithmetic)
IEEE Transactions on Computers
Design of a Radix 4 Division Unit with Simple Selection Table
IEEE Transactions on Computers
The CORDIC Algorithm: New Results for Fast VLSI Implementation
IEEE Transactions on Computers
IEEE Transactions on Computers
Systematic Design of Pipelined Recursive Filters
IEEE Transactions on Computers
Over-Redundant Digit Sets and the Design of Digit-By-Digit Division Units
IEEE Transactions on Computers
Digit-Set Conversions: Generalizations and Applications
IEEE Transactions on Computers
High-Radix Division and Square-Root with Speculation
IEEE Transactions on Computers
A Fast Radix-4 Division Algorithm and its Architecture
IEEE Transactions on Computers
Choices of Operand Truncation in the SRT Division Algorithm
IEEE Transactions on Computers
IEEE Transactions on Computers
FPGA-Based Structures for On-Line FFT and DCT
FCCM '99 Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Self timed division and square-root extraction
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
A New Divide and Conquer Method for Achieving High Speed Division in Hardware
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Synthesis and verification
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Algorithm and Architecture for Logarithm, Exponential, and Powering Computation
IEEE Transactions on Computers
Digit Selection for SRT Division and Square Root
IEEE Transactions on Computers
High-Radix Logarithm with Selection by Rounding: Algorithm and Implementation
Journal of VLSI Signal Processing Systems
High Speed Redundant Adder and Divider in Output Prediction Logic
ISVLSI '05 Proceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design
Truncated Online Arithmetic with Applications to Communication Systems
IEEE Transactions on Computers
A Digit-by-Digit Algorithm for mth Root Extraction
IEEE Transactions on Computers
A Novel Redundant Binary Number to Natural Binary Number Converter
Journal of Signal Processing Systems
A new compact SD2 positive integer triangular array division circuit
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Hi-index | 15.07 |
An algorithm to convert redundant number representations into conventional representations is presented. The algorithm is performed concurrently with the digit-by-digit generation of redundant forms by schemes such as SRT division. It has a step delay roughly equivalent to the delay of a carry-save adder and simple implementation. The conversion scheme is applicable in arithmetic algorithms such as nonrestoring division, square root, and on-line operations in which redundantly represented results are generated in a digit-by-digit manner, from most significant to least significant.