Principles of CMOS VLSI design: a systems perspective
Principles of CMOS VLSI design: a systems perspective
On-the-fly conversion of redundant into conventional representations
IEEE Transactions on Computers
High-Speed VLSI Arithmetic Processor Architectures Using Hybrid Number Representation
ICCD '91 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
A Systematic Methodology for the Design of High Performance Recursive Digital Filters
IEEE Transactions on Computers
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Systematic design of pipelined recursive filters is presented. The procedure is based on a multiplication algorithm which generates the result with most significant digit first. Since the latency of such a multiplier is low, a reduced number of pipelining delays may be introduced in the reduction loop, resulting in a high sampling rate. The implementation obtained exhibits minimum hardware and ensures minimum latency. It is shown that its flexibility allows, on one hand, the ability to choose freely the number system radix and, on the other hand, the interleaving of two multiplier arrays into one. This is illustrated by the realization of a second-order all-pole filter, operating in a radix-4 representation and using only one array to perform two multiplications. In this way, long interconnections are avoided and denser and more regular layout is achieved. It turns out that the design procedure can also be applied successfully to various types of realization where multiplications are required.