Digital Signal Processing
Fast Multiplication Without Carry-Propagate Addition
IEEE Transactions on Computers
On the use of most significant digit first arithmetic in the design of high performance DSP chips
Proceedings of the international workshop on Algorithms and parallel VLSI architectures II
High performance VLSI architecture for Wave Digital Filtering
Journal of VLSI Signal Processing Systems
Systematic Design of Pipelined Recursive Filters
IEEE Transactions on Computers
Reduction of latency and resource usage in bit-level pipelined data paths for FPGAs
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
From Bit Level Systolic Arrays to HDTV Processor Chips
Journal of Signal Processing Systems
On line wavelets transform on a Xilinx FPGA circuit to medical images compression
SSIP'08 Proceedings of the 8th conference on Signal, Speech and image processing
| Hi-index | 14.98 |
A systematic design methodology is described for the rapid derivation of VLSI architectures for implementing high performance recursive digital filters, particularly ones based on most significant digit (msd) first arithmetic. The method has been derived by undertaking theoretical investigations of msd first multiply-accumulate algorithms and by deriving important relationships governing the dependencies between circuit latency, levels of pipelining and the range and number representations of filter operands. The techniques described are general and can be applied to both bit parallel and bit serial circuits, including those based on on-line arithmetic. The method is illustrated by applying it to the design of a number of highly pipelined bit parallel IIR and wave digital filter circuits. It is shown that established architectures, which were previously designed using heuristic techniques, can be derived directly from the equations described.