On-the-fly conversion of redundant into conventional representations
IEEE Transactions on Computers
Carry-Save Multiplication Schemes Without Final Addition
IEEE Transactions on Computers
A High-Speed Reduced-Size Adder Under Left-to-Right Input Arrival
IEEE Transactions on Computers
High-Speed Booth Encoded Parallel Multiplier Design
IEEE Transactions on Computers - Special issue on computer arithmetic
On-the-Fly Rounding (Computing Arithmetic)
IEEE Transactions on Computers
Over-Redundant Digit Sets and the Design of Digit-By-Digit Division Units
IEEE Transactions on Computers
High-Radix Division and Square-Root with Speculation
IEEE Transactions on Computers
A Systematic Methodology for the Design of High Performance Recursive Digital Filters
IEEE Transactions on Computers
Bit-level two's complement matrix multiplication
Integration, the VLSI Journal
Low-power fixed-width array multipliers
Proceedings of the 2004 international symposium on Low power electronics and design
Algorithm and Architecture for Logarithm, Exponential, and Powering Computation
IEEE Transactions on Computers
High-Performance Low-Power Left-to-Right Array Multiplier Design
IEEE Transactions on Computers
The delay of circuits whose inputs have specified arrival times
Discrete Applied Mathematics
Complex Square Root with Operand Prescaling
Journal of VLSI Signal Processing Systems
Low Complexity Reconfigurable DSP Circuit Implementations Based on Common Sub-expression Elimination
Journal of Signal Processing Systems
Signed multiplication technique by means of unsigned multiply instruction
Computers and Electrical Engineering
| Hi-index | 15.01 |
Conventional schemes for fast multiplication accumulate the partial products in redundant form (carry-save or signed-digit) and convert the result to conventional representation in the last step. This step requires a carry-propagate adder which is comparatively slow and occupies a significant area of the chip in a VLSI implementation. A report is presented on a multiplication scheme (left-to-right, carry-free, LRCF) that does not require this carry-propagate step. The LRCF scheme performs the multiplication most-significant bit first and produces a conventional sign-and-magnitude product (most significant n bits) by means of an on-the-fly conversion. The resulting implementation is fast and regular and is very well suited for VLSI. The LRCF scheme for general radix r and a radix-4 signed-digit implementation are presented.