Principles of CMOS VLSI design: a systems perspective
Principles of CMOS VLSI design: a systems perspective
Fast Multiplication Without Carry-Propagate Addition
IEEE Transactions on Computers
Computer arithmetic algorithms
Computer arithmetic algorithms
Minimizing energy dissipation in high-speed multipliers
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
Optimal Circuits for Parallel Multipliers
IEEE Transactions on Computers
Computer Arithmetic: Principles, Architecture and Design
Computer Arithmetic: Principles, Architecture and Design
An Algorithmic Approach for Generic Parallel Adders
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Low-power fixed-width array multipliers
Proceedings of the 2004 international symposium on Low power electronics and design
High-Performance Low-Power Left-to-Right Array Multiplier Design
IEEE Transactions on Computers
Integrated algorithmic logical and physical design of integer multiplier
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A Simple High-Speed Multiplier Design
IEEE Transactions on Computers
A low-power multiplier with the spurious power suppression technique
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A high-speed radix-4 multiplexer-based array multiplier
Proceedings of the 18th ACM Great Lakes symposium on VLSI
High speed pipelined Booth multiplier for DSP applications
ICC'05 Proceedings of the 9th International Conference on Circuits
Partial product reduction by using look-up tables for M×N multiplier
Integration, the VLSI Journal
Flexible multi-mode embedded floating-point unit for field programmable gate arrays
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
Modified booth multipliers with a regular partial product array
IEEE Transactions on Circuits and Systems II: Express Briefs
Custom floating-point unit generation for embedded systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A spurious-power suppression technique for multimedia/DSP applications
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Multiplication acceleration through twin precision
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Dual channel addition based FFT processor architecture for signal and image processing
International Journal of High Performance Systems Architecture
High-accuracy fixed-width modified booth multipliers for lossy applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Circuits and Systems Part I: Regular Papers - Special section on 2009 IEEE system-on-chip conference
A micropower low-voltage multiplier with reduced spurious switching
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A logarithmic time method for two's complementation
ICCS'05 Proceedings of the 5th international conference on Computational Science - Volume Part I
Low power energy efficient pipelined multiply-accumulate architecture
Proceedings of the International Conference on Advances in Computing, Communications and Informatics
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This paper presents a design methodology for high-speed Booth encoded parallel multiplier. For partial product generation, we propose a new modified Booth encoding (MBE) scheme to improve the performance of traditional MBE schemes. For final addition, a new algorithm is developed to construct multiple-level conditional-sum adder (MLCSMA). The proposed algorithm can optimize final adder according to the given cell properties and input delay profile. Compared with a binary tree-based conditional-sum adder, the speed performance improvement is up to 25 percent. On average, the design developed herein reduces the total delay by 8 percent for parallel multiplier. The whole design has been verified by gate level simulation.