High speed pipelined Booth multiplier for DSP applications

Authors:
Hwang-Cherng Chow;I-Chyn Wey
Affiliations:
Department and Graduate Institute of Electronics Engineering, Chang Gung University, Taiwan, Republic of China;Department and Graduate Institute of Electronics Engineering, Chang Gung University, Taiwan, Republic of China
Venue:
ICC'05 Proceedings of the 9th International Conference on Circuits
Year:
2005

Citing 3
Cited 0

Basic VLSI design (3rd ed.)

Basic VLSI design (3rd ed.)
Minimizing energy dissipation in high-speed multipliers

ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
High-Speed Booth Encoded Parallel Multiplier Design

IEEE Transactions on Computers - Special issue on computer arithmetic

Quantified Score

Hi-index	0.01

Visualization

Abstract

In this paper, a new MBE (modified Booth encoding) recoder, and a new MBE decoder are proposed in CMOS transistor level to improve the performance of traditional multipliers. The proposed pipelined Booth multiplier can reduce the delay time of the critical path by levelizing the complex gate in the MBE decoder. As a result, MBE decoder is no more the speed bottleneck of a pipelined booth multiplier, and the speed of the MBE decoder can be improved up to 66.3 percent. Besides, an 8-bit by 8-bit glitch-free Booth multiplier is pipelined as a traditional pipelined array multiplier without any bottleneck in the MBE encoder and decoder, but with better performance in both power and speed. Finally, a low voltage, high speed pipelined glitch-free Booth multiplier architecture is presented at 1 GHz in TSMC 0.35µm process with a power consumption of only 100.52mw.