An Approach to Implementing Multiplication with Small Tables
IEEE Transactions on Computers
Fast multiplication: algorithms and implementation
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IEEE Transactions on Computers
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IEEE Transactions on Computers
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IEEE Transactions on Computers
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IEEE Transactions on Computers
Integration, the VLSI Journal
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Embedded Memories for the Future
IEEE Design & Test
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IEEE Transactions on Computers
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ARITH '05 Proceedings of the 17th IEEE Symposium on Computer Arithmetic
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IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation
Mathematical model of stored logic based computation
Mathematical and Computer Modelling: An International Journal
International Journal of High Performance Systems Architecture
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In this paper we present a new technique for partial product reduction in multiplication operations. The method is based on the construction of counter elements by means of look-up tables. The organization of these counters into reduction trees takes advantage of the inherent benefits of the integration of the memories and provides an alternative to classic operation methods. We show several reduction schemes that illustrate the proposed technique and describe hybrid examples that combine stored logic with classic combinational counters in order to adapt them better to each scheme. Our approach outperforms other schemes used for comparison. In this sense, not only an independent technology model has been established, but also an FPGA approximation has been implemented to measure such factors in a real-life technology platform.