FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
Extensible multiplier-accumulator blocks for FPGAs
WISICT '05 Proceedings of the 4th international symposium on Information and communication technologies
Some Optimizations of Hardware Multiplication by Constant Matrices
IEEE Transactions on Computers
Termination of Floating-Point Computations
Journal of Automated Reasoning
Integrated algorithmic logical and physical design of integer multiplier
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Real-Time Systems
A Decimal Floating-Point Divider Using Newton---Raphson Iteration
Journal of VLSI Signal Processing Systems
A Tool for Unbiased Comparison between Logarithmic and Floating-point Arithmetic
Journal of VLSI Signal Processing Systems
Efficient implementation of 3X for radix-8 encoding
Microelectronics Journal
Analog Integrated Circuits and Signal Processing
Efficient implementation of constant coefficient division under quantization constraints
ICC'05 Proceedings of the 9th International Conference on Circuits
Partial product reduction by using look-up tables for M×N multiplier
Integration, the VLSI Journal
Low-error, High-speed Approximation of the Sigmoid Function for Large FPGA Implementations
Journal of Signal Processing Systems
Higher radix and redundancy factor for floating point SRT division
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Reconfigurable custom floating-point instructions (abstract only)
Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays
High-performance hardware operators for polynomial evaluation
International Journal of High Performance Systems Architecture
Reduced redundant arithmetic applied on low power multiply-accumulate units
EHAC'12/ISPRA/NANOTECHNOLOGY'12 Proceedings of the 11th WSEAS international conference on Electronics, Hardware, Wireless and Optical Communications, and proceedings of the 11th WSEAS international conference on Signal Processing, Robotics and Automation, and proceedings of the 4th WSEAS international conference on Nanotechnology
VHDL code generator for optimized carry-save reduction strategy in low power computer arithmetic
CSCC'11 Proceedings of the 2nd international conference on Circuits, Systems, Communications & Computers
On carry-save strategies for multiply-accumulate arithmetic
CSCC'11 Proceedings of the 2nd international conference on Circuits, Systems, Communications & Computers
Optimized Hardware Implementation for Forward Quantization of H.264/AVC
Journal of Signal Processing Systems
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From the Publisher:The book covers recent advances in the design of computer arithmetic units. This becomes an increasingly timely issue as the underlying silicon technology enables designers to capture more system functions on fewer silicon dies. The particular functions of interest include multimedia (video and audio) applications, 3-D graphic figure manipulation, wireless communications and encrypting messages.